ARM: dts: Add UART2 dt node for Exynos3250 SoC 99/45699/1
authorChanwoo Choi <cw00.choi@samsung.com>
Fri, 17 Jul 2015 05:49:08 +0000 (14:49 +0900)
committerChanwoo Choi <cw00.choi@samsung.com>
Mon, 10 Aug 2015 12:09:15 +0000 (21:09 +0900)
This patch add the uart2 devicetree node for Exynos3250 SoC.

Change-Id: I28dd84bc645e26f14b7d0c7d630870cc812dccd8
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
arch/arm/boot/dts/exynos3250-pinctrl.dtsi
arch/arm/boot/dts/exynos3250.dtsi

index 5ab81c39e2c9ca8bcd21e1cb14559e2e0166837a..eac1d21c10d4eba5649198c7052880b233754588 100644 (file)
                samsung,pin-drv = <0>;
        };
 
+       uart2_data: uart2-data {
+               samsung,pins = "gpa1-0", "gpa1-1";
+               samsung,pin-function = <2>;
+               samsung,pin-pud = <0>;
+               samsung,pin-drv = <0>;
+       };
+
        i2c3_bus: i2c3-bus {
                samsung,pins = "gpa1-2", "gpa1-3";
                samsung,pin-function = <3>;
index ac6b0ae42caff5f9ad7d14307f2421ddbf35c689..a2094083022bf4e32afbaf46cb67538ac3331a78 100644 (file)
@@ -42,6 +42,7 @@
                i2c7 = &i2c_7;
                serial0 = &serial_0;
                serial1 = &serial_1;
+               serial2 = &serial_2;
        };
 
        cpus {
                        status = "disabled";
                };
 
+               serial_2: serial@13820000 {
+                       compatible = "samsung,exynos4210-uart";
+                       reg = <0x13820000 0x100>;
+                       interrupts = <0 111 0>;
+                       clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+                       clock-names = "uart", "clk_uart_baud0";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_data>;
+                       status = "disabled";
+               };
+
                i2c_0: i2c@13860000 {
                        #address-cells = <1>;
                        #size-cells = <0>;