dmaengine: PL08x: get rid of unnecessary checks in dma_slave_config

Get rid of the unnecessary checks in dma_slave_config utilizing
the DMA direction.  This allows us to move the computation of
cctl to the prepare function.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 0f882ec..6ec3005 100644 (file)
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -120,182 +120,156 @@ struct pl08x_channel_data spear300_dma_info[] = {
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart0_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "irda",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "adc",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "to_jpeg",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "from_jpeg",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras0_rx",
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras0_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras1_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras1_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras2_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras2_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras3_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras3_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras4_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras4_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_rx",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_tx",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_rx",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_tx",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        },
 };

diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index bbcf457..1d0e435 100644 (file)
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -205,182 +205,156 @@ struct pl08x_channel_data spear310_dma_info[] = {
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart0_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "irda",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "adc",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "to_jpeg",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "from_jpeg",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart1_rx",
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart1_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart2_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart2_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart3_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart3_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart4_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart4_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart5_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart5_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_rx",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_tx",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_rx",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_tx",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        },
 };

diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 88d483b..fd823c6 100644 (file)
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -213,182 +213,156 @@ struct pl08x_channel_data spear320_dma_info[] = {
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart0_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c0_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c0_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "irda",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "adc",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "to_jpeg",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "from_jpeg",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp1_rx",
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ssp1_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ssp2_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ssp2_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "uart1_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "uart1_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "uart2_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "uart2_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2c1_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2c1_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2c2_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2c2_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2s_rx",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "i2s_tx",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "rs485_rx",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "rs485_tx",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        },
 };

diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 0f41bd1..d6cd840 100644 (file)
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -46,7 +46,8 @@ struct pl022_ssp_controller pl022_plat_data = {
 struct pl08x_platform_data pl080_plat_data = {
        .memcpy_channel = {
                .bus_id = "memcpy",
-               .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+               .cctl_memcpy =
+                       (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \

diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2e2e359..b59ae53 100644 (file)
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -36,336 +36,288 @@ static struct pl08x_channel_data spear600_dma_info[] = {
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp1_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart0_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart0_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart1_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "uart1_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp2_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ssp2_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ssp0_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ssp0_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "i2c_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "irda",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "adc",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "to_jpeg",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "from_jpeg",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 0,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras0_rx",
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras0_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras1_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras1_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras2_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras2_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras3_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras3_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras4_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras4_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras5_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_rx",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras6_tx",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_rx",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ras7_tx",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 1,
-               .cctl = 0,
                .periph_buses = PL08X_AHB1,
        }, {
                .bus_id = "ext0_rx",
                .min_signal = 0,
                .max_signal = 0,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext0_tx",
                .min_signal = 1,
                .max_signal = 1,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext1_rx",
                .min_signal = 2,
                .max_signal = 2,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext1_tx",
                .min_signal = 3,
                .max_signal = 3,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext2_rx",
                .min_signal = 4,
                .max_signal = 4,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext2_tx",
                .min_signal = 5,
                .max_signal = 5,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext3_rx",
                .min_signal = 6,
                .max_signal = 6,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext3_tx",
                .min_signal = 7,
                .max_signal = 7,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext4_rx",
                .min_signal = 8,
                .max_signal = 8,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext4_tx",
                .min_signal = 9,
                .max_signal = 9,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext5_rx",
                .min_signal = 10,
                .max_signal = 10,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext5_tx",
                .min_signal = 11,
                .max_signal = 11,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext6_rx",
                .min_signal = 12,
                .max_signal = 12,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext6_tx",
                .min_signal = 13,
                .max_signal = 13,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext7_rx",
                .min_signal = 14,
                .max_signal = 14,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        }, {
                .bus_id = "ext7_tx",
                .min_signal = 15,
                .max_signal = 15,
                .muxval = 2,
-               .cctl = 0,
                .periph_buses = PL08X_AHB2,
        },
 };
@@ -373,7 +325,8 @@ static struct pl08x_channel_data spear600_dma_info[] = {
 struct pl08x_platform_data pl080_plat_data = {
        .memcpy_channel = {
                .bus_id = "memcpy",
-               .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+               .cctl_memcpy =
+                       (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 50b9a83..f739778 100644 (file)
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -235,8 +235,6 @@ struct pl08x_dma_chan {
        const char *name;
        const struct pl08x_channel_data *cd;
        struct dma_slave_config cfg;
-       u32 src_cctl;
-       u32 dst_cctl;
        struct list_head pend_list;
        struct pl08x_txd *at;
        spinlock_t lock;
@@ -1235,30 +1233,15 @@ static int dma_set_runtime_config(struct dma_chan *chan,
                                  struct dma_slave_config *config)
 {
        struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
-       struct pl08x_driver_data *pl08x = plchan->host;
-       u32 src_cctl, dst_cctl;
 
        if (!plchan->slave)
                return -EINVAL;
 
-       dst_cctl = pl08x_get_cctl(plchan, config->dst_addr_width,
-                                 config->dst_maxburst);
-       if (dst_cctl == ~0 && config->direction == DMA_MEM_TO_DEV) {
-               dev_err(&pl08x->adev->dev,
-                       "bad runtime_config: alien address width (M2D)\n");
+       /* Reject definitely invalid configurations */
+       if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
+           config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
                return -EINVAL;
-       }
 
-       src_cctl = pl08x_get_cctl(plchan, config->src_addr_width,
-                                 config->src_maxburst);
-       if (src_cctl == ~0 && config->direction == DMA_DEV_TO_MEM) {
-               dev_err(&pl08x->adev->dev,
-                       "bad runtime_config: alien address width (D2M)\n");
-               return -EINVAL;
-       }
-
-       plchan->dst_cctl = dst_cctl;
-       plchan->src_cctl = src_cctl;
        plchan->cfg = *config;
 
        return 0;
@@ -1407,7 +1390,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 
        /* Set platform data for m2m */
        txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
-       txd->cctl = pl08x->pd->memcpy_channel.cctl &
+       txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy &
                        ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
 
        /* Both to be incremented or the code will break */
@@ -1434,10 +1417,11 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
        struct pl08x_txd *txd;
        struct pl08x_sg *dsg;
        struct scatterlist *sg;
+       enum dma_slave_buswidth addr_width;
        dma_addr_t slave_addr;
        int ret, tmp;
        u8 src_buses, dst_buses;
-       u32 cctl;
+       u32 maxburst, cctl;
 
        dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
                        __func__, sg_dma_len(sgl), plchan->name);
@@ -1456,13 +1440,17 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
        txd->direction = direction;
 
        if (direction == DMA_MEM_TO_DEV) {
-               cctl = plchan->dst_cctl | PL080_CONTROL_SRC_INCR;
+               cctl = PL080_CONTROL_SRC_INCR;
                slave_addr = plchan->cfg.dst_addr;
+               addr_width = plchan->cfg.dst_addr_width;
+               maxburst = plchan->cfg.dst_maxburst;
                src_buses = pl08x->mem_buses;
                dst_buses = plchan->cd->periph_buses;
        } else if (direction == DMA_DEV_TO_MEM) {
-               cctl = plchan->src_cctl | PL080_CONTROL_DST_INCR;
+               cctl = PL080_CONTROL_DST_INCR;
                slave_addr = plchan->cfg.src_addr;
+               addr_width = plchan->cfg.src_addr_width;
+               maxburst = plchan->cfg.src_maxburst;
                src_buses = plchan->cd->periph_buses;
                dst_buses = pl08x->mem_buses;
        } else {
@@ -1472,6 +1460,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
                return NULL;
        }
 
+       cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
        if (cctl == ~0) {
                pl08x_free_txd(pl08x, txd);
                dev_err(&pl08x->adev->dev,
@@ -1774,14 +1763,10 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
 
 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
 {
-       u32 cctl = pl08x_cctl(chan->cd->cctl);
-
        chan->slave = true;
        chan->name = chan->cd->bus_id;
        chan->cfg.src_addr = chan->cd->addr;
        chan->cfg.dst_addr = chan->cd->addr;
-       chan->src_cctl = cctl;
-       chan->dst_cctl = cctl;
 }
 
 /*

diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 158ce26..2a5f64a 100644 (file)
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -47,7 +47,8 @@ enum {
  * devices with static assignments
  * @muxval: a number usually used to poke into some mux regiser to
  * mux in the signal to this channel
- * @cctl_opt: default options for the channel control register
+ * @cctl_memcpy: options for the channel control register for memcpy
+ *  *** not used for slave channels ***
  * @addr: source/target address in physical memory for this DMA channel,
  * can be the address of a FIFO register for burst requests for example.
  * This can be left undefined if the PrimeCell API is used for configuring
@@ -62,7 +63,7 @@ struct pl08x_channel_data {
        int min_signal;
        int max_signal;
        u32 muxval;
-       u32 cctl;
+       u32 cctl_memcpy;
        dma_addr_t addr;
        bool single;
        u8 periph_buses;