; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-quadword-atomics -mcpu=pwr8 %s | FileCheck %s
+; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 %s | FileCheck --check-prefix=PWR7 %s
define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
; CHECK-LABEL: @test_cmpxchg_seq_cst(
; CHECK-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1
; CHECK-NEXT: ret i1 [[SUCC]]
;
+; PWR7-LABEL: @test_cmpxchg_seq_cst(
+; PWR7-NEXT: entry:
+; PWR7-NEXT: call void @llvm.ppc.sync()
+; PWR7-NEXT: [[PAIR:%.*]] = cmpxchg weak i128* [[ADDR:%.*]], i128 [[DESIRE:%.*]], i128 [[NEW:%.*]] monotonic monotonic, align 16
+; PWR7-NEXT: call void @llvm.ppc.lwsync()
+; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[PAIR]], 1
+; PWR7-NEXT: ret i1 [[SUCC]]
+;
entry:
%pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst
%succ = extractvalue {i128, i1} %pair, 1