phy: micrel: Add definitions for common Micrel PHY registers
authorDinh Nguyen <dinguyen@altera.com>
Tue, 13 Aug 2013 14:59:00 +0000 (09:59 -0500)
committerShawn Guo <shawn.guo@linaro.org>
Thu, 22 Aug 2013 15:20:54 +0000 (23:20 +0800)
Add defines for common Micrel PHY setups so that other platforms
can use them. Update imx61 and sama5 hardware to use the micrel_phy.h
PHY defines.

Also add support for the KSZ9021RLRN PHY.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: Andrew Victor <linux@maxim.org.za>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: netdev@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/mach-at91/board-dt-sama5.c
arch/arm/mach-imx/mach-imx6q.c
include/linux/micrel_phy.h

index ad95f6a..bf00d15 100644 (file)
@@ -42,20 +42,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
        int value;
 
-#define GMII_RCCPSR    260
-#define GMII_RRDPSR    261
-#define GMII_ERCR      11
-#define GMII_ERDWR     12
-
        /* Set delay values */
-       value = GMII_RCCPSR | 0x8000;
-       phy_write(phy, GMII_ERCR, value);
+       value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
+       phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
        value = 0xF2F4;
-       phy_write(phy, GMII_ERDWR, value);
-       value = GMII_RRDPSR | 0x8000;
-       phy_write(phy, GMII_ERCR, value);
+       phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
+       value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
+       phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
        value = 0x2222;
-       phy_write(phy, GMII_ERDWR, value);
+       phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
 
        return 0;
 }
index c730af6..1e093ab 100644 (file)
@@ -103,13 +103,16 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
        if (IS_BUILTIN(CONFIG_PHYLIB)) {
                /* min rx data delay */
-               phy_write(phydev, 0x0b, 0x8105);
-               phy_write(phydev, 0x0c, 0x0000);
+               phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                       0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
+               phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
 
                /* max rx/tx clock delay, min rx/tx control delay */
-               phy_write(phydev, 0x0b, 0x8104);
-               phy_write(phydev, 0x0c, 0xf0f0);
-               phy_write(phydev, 0x0b, 0x104);
+               phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                       0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
+               phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
+               phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                       MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
        }
 
        return 0;
index 8752dbb..ad05ce6 100644 (file)
@@ -17,6 +17,7 @@
 
 #define PHY_ID_KSZ8873MLL      0x000e7237
 #define PHY_ID_KSZ9021         0x00221610
+#define PHY_ID_KSZ9021RLRN     0x00221611
 #define PHY_ID_KS8737          0x00221720
 #define PHY_ID_KSZ8021         0x00221555
 #define PHY_ID_KSZ8031         0x00221556
@@ -35,4 +36,9 @@
 /* struct phy_device dev_flags definitions */
 #define MICREL_PHY_50MHZ_CLK   0x00000001
 
+#define MICREL_KSZ9021_EXTREG_CTRL     0xB
+#define MICREL_KSZ9021_EXTREG_DATA_WRITE       0xC
+#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
+#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW  0x105
+
 #endif /* _MICREL_PHY_H */