spi: dw: Add support for Intel Thunder Bay SPI controller

Add support for Intel Thunder Bay SPI controller, which uses DesignWare
DWC_ssi core and also add common init function for both Keem Bay and
Thunder Bay.

Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 5101c4c..26c40ea 100644 (file)
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev,
        return 0;
 }
 
-static int dw_spi_keembay_init(struct platform_device *pdev,
-                              struct dw_spi_mmio *dwsmmio)
+static int dw_spi_intel_init(struct platform_device *pdev,
+                            struct dw_spi_mmio *dwsmmio)
 {
        dwsmmio->dws.ip = DW_HSSI_ID;
-       dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;
 
        return 0;
 }
@@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
        { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
        { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
        { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
-       { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
+       { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
+       { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
        { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
        { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
        { /* end of table */}

diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 8b8f924..9e8eb2b 100644 (file)
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -31,8 +31,7 @@
 
 /* DW SPI controller capabilities */
 #define DW_SPI_CAP_CS_OVERRIDE         BIT(0)
-#define DW_SPI_CAP_KEEMBAY_MST         BIT(1)
-#define DW_SPI_CAP_DFS32               BIT(2)
+#define DW_SPI_CAP_DFS32               BIT(1)
 
 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
 #define DW_SPI_CTRLR0                  0x00