dt-bindings: net: add pcs-handle attribute

Document the new pcs-handle attribute to support connecting to an
external PHY. For Xilinx's AXI Ethernet, this is used when the core
operates in SGMII or 1000Base-X modes and links through the internal
PCS/PMA PHY.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 817794e..4f15463 100644 (file)
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -106,6 +106,12 @@ properties:
   phy-mode:
     $ref: "#/properties/phy-connection-type"
 
+  pcs-handle:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Specifies a reference to a node representing a PCS PHY device on a MDIO
+      bus to link with an external PHY (phy-handle) if exists.
+
   phy-handle:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:

diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index b8e4894..1aa4c60 100644 (file)
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
@@ -26,7 +26,8 @@ Required properties:
                  specified, the TX/RX DMA interrupts should be on that node
                  instead, and only the Ethernet core interrupt is optionally
                  specified here.
-- phy-handle   : Should point to the external phy device.
+- phy-handle   : Should point to the external phy device if exists. Pointing
+                 this to the PCS/PMA PHY is deprecated and should be avoided.
                  See ethernet.txt file in the same directory.
 - xlnx,rxmem   : Set to allocated memory buffer for Rx/Tx in the hardware
 
@@ -68,6 +69,11 @@ Optional properties:
                  required through the core's MDIO interface (i.e. always,
                  unless the PHY is accessed through a different bus).
 
+ - pcs-handle:           Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
+                 modes, where "pcs-handle" should be used to point
+                 to the PCS/PMA PHY, and "phy-handle" should point to an
+                 external PHY if exists.
+
 Example:
        axi_ethernet_eth: ethernet@40c00000 {
                compatible = "xlnx,axi-ethernet-1.00.a";