clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics

This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index b969376..c0d9271 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -189,13 +189,13 @@ static const struct clk_pll_layout pll_layout_divio = {
 /* MCK0 characteristics. */
 static const struct clk_master_characteristics mck0_characteristics = {
        .output = { .min = 140000000, .max = 200000000 },
-       .divisors = { 1, 2, 4, 3 },
+       .divisors = { 1, 2, 4, 3, 5 },
        .have_div3_pres = 1,
 };
 
 /* MCK0 layout. */
 static const struct clk_master_layout mck0_layout = {
-       .mask = 0x373,
+       .mask = 0x773,
        .pres_shift = 4,
        .offset = 0x28,
 };