This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.
opcodes/
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
gas/testsuite/
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
* gas/ppc/power4.d: Likewise.
810: (7e 95 01 90|90 01 95 7e) subfze r20,r21
814: (7e 95 05 91|91 05 95 7e) subfzeo\. r20,r21
818: (7e 95 05 90|90 05 95 7e) subfzeo r20,r21
- 81c: (7c 00 04 ac|ac 04 00 7c) sync
- 820: (7c 00 04 ac|ac 04 00 7c) sync
- 824: (7c 00 04 ac|ac 04 00 7c) sync
+ 81c: (7c 00 04 ac|ac 04 00 7c) hwsync
+ 820: (7c 00 04 ac|ac 04 00 7c) hwsync
+ 824: (7c 00 04 ac|ac 04 00 7c) hwsync
828: (7c 20 04 ac|ac 04 20 7c) lwsync
82c: (7c aa 58 88|88 58 aa 7c) tdlge r10,r11
830: (08 aa 00 64|64 00 aa 08) tdlgei r10,100
Sections:
Idx Name +Size +VMA +LMA +File off +Algn
- +0 \.text +0+cc +0+ +0+ +.*
+ +0 \.text +0+e8 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+1 \.data +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA
.*: (f8 05 00 12|12 00 05 f8) stq r0,16\(r5\)
.*: (f8 45 00 12|12 00 45 f8) stq r2,16\(r5\)
.*: (7c 00 03 e4|e4 03 00 7c) slbia
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 20 04 ac|ac 04 20 7c) lwsync
+.*: (7c 20 04 ac|ac 04 20 7c) lwsync
+.*: (7c 40 04 ac|ac 04 40 7c) ptesync
+.*: (7c 40 04 ac|ac 04 40 7c) ptesync
stq 0,16(5)
stq 2,16(5)
slbia
+ hwsync
+ sync
+ sync 0
+ lwsync
+ sync 1
+ ptesync
+ sync 2
.section ".data"
usym0: .llong 0xcafebabe
{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
+{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},