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imx: imx8m: clock: not configure reserved SRC register
author
Peng Fan
<peng.fan@nxp.com>
Thu, 15 Jun 2023 10:09:21 +0000
(18:09 +0800)
committer
Stefano Babic
<sbabic@denx.de>
Thu, 13 Jul 2023 09:29:40 +0000
(11:29 +0200)
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/mach-imx/imx8m/clock_imx8mm.c
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diff --git
a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index
31c34b6
..
9868707
100644
(file)
--- a/
arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/
arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@
-90,7
+90,6
@@
static int fracpll_configure(enum pll_clocks pll, u32 freq)
case ANATOP_DRAM_PLL:
setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
- writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
pll_base = &ana_pll->dram_pll_gnrl_ctl;
break;