arm64: dts: qcom: sm6375: Introduce C3 power state for both ARM clusters

Introduce the C3 power state, which - to the best of my understanding -
gates the CPU clock, but does not shut off the power rail.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-13-708b8191f7eb@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 6b75d86..f66f7ec 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -214,6 +214,16 @@
                idle-states {
                        entry-method = "psci";
 
+                       LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+                               compatible = "arm,idle-state";
+                               idle-state-name = "silver-power-collapse";
+                               arm,psci-suspend-param = <0x40000003>;
+                               entry-latency-us = <549>;
+                               exit-latency-us = <901>;
+                               min-residency-us = <1774>;
+                               local-timer-stop;
+                       };
+
                        LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
                                compatible = "arm,idle-state";
                                idle-state-name = "silver-rail-power-collapse";
@@ -224,6 +234,16 @@
                                local-timer-stop;
                        };
 
+                       BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+                               compatible = "arm,idle-state";
+                               idle-state-name = "gold-power-collapse";
+                               arm,psci-suspend-param = <0x40000003>;
+                               entry-latency-us = <523>;
+                               exit-latency-us = <1244>;
+                               min-residency-us = <2207>;
+                               local-timer-stop;
+                       };
+
                        BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
                                compatible = "arm,idle-state";
                                idle-state-name = "gold-rail-power-collapse";
@@ -275,49 +295,49 @@
                CPU_PD0: power-domain-cpu0 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD1: power-domain-cpu1 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD2: power-domain-cpu2 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD3: power-domain-cpu3 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD4: power-domain-cpu4 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD5: power-domain-cpu5 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD6: power-domain-cpu6 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&BIG_CPU_SLEEP_1>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                };
 
                CPU_PD7: power-domain-cpu7 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&BIG_CPU_SLEEP_1>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                };
 
                CLUSTER_PD: power-domain-cpu-cluster0 {