drm/amd/display: Clean up flip pending timeout handling

[Why]
Adjust timeout handling code for easier runtime manipulation
during debug. Change has no functional effect by default.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index e0a73d9..fc1af33 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1269,20 +1269,21 @@ void dcn20_pipe_control_lock(
        }
 
        if (flip_immediate && lock) {
-               const int TIMEOUT_FOR_FLIP_PENDING = 100000;
+               const int TIMEOUT_FOR_FLIP_PENDING_US = 100000;
+               unsigned int polling_interval_us = 1;
                int i;
 
                temp_pipe = pipe;
                while (temp_pipe) {
                        if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) {
-                               for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
+                               for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING_US / polling_interval_us; ++i) {
                                        if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))
                                                break;
-                                       udelay(1);
+                                       udelay(polling_interval_us);
                                }
 
                                /* no reason it should take this long for immediate flips */
-                               ASSERT(i != TIMEOUT_FOR_FLIP_PENDING);
+                               ASSERT(i != TIMEOUT_FOR_FLIP_PENDING_US);
                        }
                        temp_pipe = temp_pipe->bottom_pipe;
                }
@@ -1952,7 +1953,8 @@ void dcn20_post_unlock_program_front_end(
                struct dc_state *context)
 {
        int i;
-       const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+       const unsigned int TIMEOUT_FOR_PIPE_ENABLE_US = 100000;
+       unsigned int polling_interval_us = 1;
        struct dce_hwseq *hwseq = dc->hwseq;
 
        DC_LOGGER_INIT(dc->ctx->logger);
@@ -1974,10 +1976,9 @@ void dcn20_post_unlock_program_front_end(
                                pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
                        struct hubp *hubp = pipe->plane_res.hubp;
                        int j = 0;
-
-                       for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
+                       for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us
                                        && hubp->funcs->hubp_is_flip_pending(hubp); j++)
-                               udelay(1);
+                               udelay(polling_interval_us);
                }
        }