drm/i915: Convert some more bits to use engine mmio accessors

Remove a couple dev_priv locals as a consequence.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190607084521.16845-1-tvrtko.ursulin@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fed704802c57ffaa7947775ab4c5ffa7fae1ea68..f27b6c002627ca2828926b7bdd2ba87e5c9b43dd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 
 static void enable_execlists(struct intel_engine_cs *engine)
 {
-       struct drm_i915_private *dev_priv = engine->i915;
-
        intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
 
-       if (INTEL_GEN(dev_priv) >= 11)
-               I915_WRITE(RING_MODE_GEN7(engine),
-                          _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+       if (INTEL_GEN(engine->i915) >= 11)
+               ENGINE_WRITE(engine,
+                            RING_MODE_GEN7,
+                            _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
        else
-               I915_WRITE(RING_MODE_GEN7(engine),
-                          _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+               ENGINE_WRITE(engine,
+                            RING_MODE_GEN7,
+                            _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 
-       I915_WRITE(RING_MI_MODE(engine->mmio_base),
-                  _MASKED_BIT_DISABLE(STOP_RING));
+       ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
 
-       I915_WRITE(RING_HWS_PGA(engine->mmio_base),
-                  i915_ggtt_offset(engine->status_page.vma));
-       POSTING_READ(RING_HWS_PGA(engine->mmio_base));
+       ENGINE_WRITE(engine,
+                    RING_HWS_PGA,
+                    i915_ggtt_offset(engine->status_page.vma));
+       ENGINE_POSTING_READ(engine, RING_HWS_PGA);
 }
 
 static bool unexpected_starting_state(struct intel_engine_cs *engine)
 {
-       struct drm_i915_private *dev_priv = engine->i915;
        bool unexpected = false;
 
-       if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
+       if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
                DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
                unexpected = true;
        }

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 550cf4b6358694f6bd039ffffc7389b770af1a2e..87be9c1b6021cf51bb41df6e70ac10269d49b74f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1713,8 +1713,9 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 
        for_each_engine(engine, dev_priv, id) {
                /* GFX_MODE is per-ring on gen7+ */
-               I915_WRITE(RING_MODE_GEN7(engine),
-                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+               ENGINE_WRITE(engine,
+                            RING_MODE_GEN7,
+                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2f85de034d8ff92d6663043b8dc33e99ec923e03..193a93857d990ef89b485598fb339f9600005dbb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
        if (HAS_PPGTT(dev_priv)) {
                int i;
 
-               ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
+               ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
 
                if (IS_GEN(dev_priv, 6)) {
                        ee->vm_info.pp_dir_base =

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7c13d5deb15132cfe2c6e4a2a6e1103e98781bd..8778f56a034cc32d4ad8016423b9b0b242ff79a4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2698,7 +2698,7 @@ enum i915_power_well_id {
 
 #define GFX_MODE       _MMIO(0x2520)
 #define GFX_MODE_GEN7  _MMIO(0x229c)
-#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
+#define RING_MODE_GEN7(base)   _MMIO((base) + 0x29c)
 #define   GFX_RUN_LIST_ENABLE          (1 << 15)
 #define   GFX_INTERRUPT_STEERING       (1 << 14)
 #define   GFX_TLB_INVALIDATE_EXPLICIT  (1 << 13)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index a4f98ccef0fe26f7dc225f7b06acbe7e631d6ad2..89592ef778b86e5488b78177eaaa3faad6398bb8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1306,7 +1306,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
         */
        irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
        for_each_engine(engine, dev_priv, id)
-               I915_WRITE(RING_MODE_GEN7(engine), irqs);
+               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
        /* route USER_INTERRUPT to Host, all others are sent to GuC. */
        irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -1353,7 +1353,7 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
        irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
        irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
        for_each_engine(engine, dev_priv, id)
-               I915_WRITE(RING_MODE_GEN7(engine), irqs);
+               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
        /* route all GT interrupts to the host */
        I915_WRITE(GUC_BCS_RCS_IER, 0);