v4l2: add isp clk tree support

v4l2: delete isp top clk configure
riscv:dts:starfive: vin add isp clk handle

Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
old mode 100644 (file)
new mode 100755 (executable)
index d6632f9..53f348d
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/reset/starfive-jh7110.h>
 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
 #include <dt-bindings/clock/starfive-jh7110-vout.h>
+#include <dt-bindings/clock/starfive-jh7110-isp.h>
 
 / {
        compatible = "starfive,jh7110";
@@ -594,12 +595,23 @@
                                <0x0 0x13020000 0x0 0x10000>;
                        reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
                                "isp0", "isp1", "trst", "pmu", "syscrg";
-                       clocks = <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
-                               <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
-                       clock-names = "clk_ispcore_2x", "clk_isp_axi";
-                       resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
-                               <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
-                               <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
+                       clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
+                               <&clkisp JH7110_U0_VIN_PCLK>,
+                               <&clkisp JH7110_U0_VIN_SYS_CLK>,
+                               <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
+                               <&clkisp JH7110_DVP_INV>,
+                               <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
+                               <&clkisp JH7110_MIPI_RX0_PXL>,
+                               <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
+                               <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
+                               <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
+                               <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
+                       clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
+                               "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
+                               "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
+                               "clk_pixel_clk_if1", "clk_pixel_clk_if2",
+                               "clk_pixel_clk_if3";
+                       resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
                                <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
                                <&rstgen RSTN_U0_VIN_N_PCLK>,
                                <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
@@ -609,10 +621,9 @@
                                <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
                                <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
                                <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>;
-                       reset-names = "rst_isp_top_n", "rst_isp_top_axi", "rst_wrapper_p",
-                               "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird",
-                               "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1",
-                               "rst_pixel_clk_if2", "rst_pixel_clk_if3";
+                       reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
+                               "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
+                               "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3";
                        interrupts = <92 87 86>;
                        status = "disabled";
                };

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
index cc6cbc0..2457a90 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
@@ -66,37 +66,34 @@ exit:
 
        return 0;
 }
+
 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
 {
        struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
        struct stfcamss *stfcamss = csi_dev->stfcamss;
 
-    reg_set_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x3<<0);
-    reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, BIT(24), 0x0<<24);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x1<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_CLK_P_AXIWR, BIT(24), 0x0<<24);
-
-#ifdef CONFIG_RESET_STARFIVE_JH7110
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
+
+#ifdef HWBOARD_FPGA
+       clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
 #else
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(4)|BIT(9));
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(10));
-    reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, BIT(11));
+       reg_set_bit(vin->clkgen_base, CLK_MIPI_RX0_PXL, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x3<<0);
 #endif
 
+       clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
+               stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
+       clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
+               stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
+
        return 0;
 }
 
@@ -105,25 +102,18 @@ static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
        struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
        struct stfcamss *stfcamss = csi_dev->stfcamss;
 
-#ifdef CONFIG_RESET_STARFIVE_JH7110
        reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
        reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
-#else
-    reg_assert_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-        BIT(6)|BIT(7)|BIT(8));
-#endif
-
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, BIT(31), 0x0<<31);
 
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF0, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF1, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF2, BIT(31), 0x0<<31);
-    reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PIXEL_CLK_IF3, BIT(31), 0x0<<31);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PCLK].clk);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
 
        return 0;
 }

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
index 4fcc3ea..74a8caa 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
@@ -9,70 +9,6 @@ static int stf_dvp_clk_init(struct stf_dvp_dev *dvp_dev)
        return 0;
 }
 
-#define U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR                        0x13040000
-void reg_phy_write(uint32_t addr,uint32_t reg,uint32_t val)
-{
-    uint32_t tmp;
-
-   iowrite32(val, ioremap(addr + reg, 4));
-}
-
-void stf_dvp_io_pad_config(struct stf_vin_dev *vin)
-{
-       /*
-        * pin: 21 ~ 35
-        * iomux
-        * SCFG_funcshare_pad_ctrl
-        */
-#if 0
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0174U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x10);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x200000);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0178U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x90);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x240000);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x017cU, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x248000);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0180U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x02a0);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0184U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x12490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x100800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0188U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x92490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x900800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x018cU, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x492490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x4900800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0190U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x2492490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x24900800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0194U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x12492490);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x248001);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0198U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x2);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x248009);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x019cU, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x12);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x248049);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x01a0U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x92);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x248249);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x01a4U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x492);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x249249);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x01a8U, 0x1);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x2492);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x24904800);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x01acU, 0x11);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x12492);
-       reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x24924800);
-#endif
-}
-
 static int stf_dvp_config_set(struct stf_dvp_dev *dvp_dev)
 {
 
@@ -89,8 +25,6 @@ static int stf_dvp_config_set(struct stf_dvp_dev *dvp_dev)
        st_info(ST_DVP, "%s, polarities = 0x%x, flags = 0x%x\n",
                        __func__, polarities, flags);
 
-       stf_dvp_io_pad_config(vin);
-
        if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
                polarities |= BIT(1);
        if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
index 4fb883b..1ce8006 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
@@ -174,7 +174,6 @@ exit_line:
        mutex_lock(&vin_dev->power_lock);
        if (on) {
                if (vin_dev->power_count == 0) {
-                       vin_dev->hw_ops->vin_power_on(vin_dev,on);
                        vin_dev->hw_ops->vin_clk_enable(vin_dev);
                        vin_dev->hw_ops->vin_config_set(vin_dev);
                }
@@ -187,7 +186,6 @@ exit_line:
                }
                if (vin_dev->power_count == 1) {
                        vin_dev->hw_ops->vin_clk_disable(vin_dev);
-                       vin_dev->hw_ops->vin_power_on(vin_dev,on);
                }
                vin_dev->power_count--;
        }

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
index 0c45597..16723e1 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
@@ -7,6 +7,7 @@
 #include <media/v4l2-async.h>
 #include <media/v4l2-fwnode.h>
 #include <media/v4l2-subdev.h>
+#include <linux/clk-provider.h>
 
 static int vin_rstgen_assert_reset(struct stf_vin_dev *vin)
 {
@@ -103,43 +104,32 @@ static int stf_vin_clk_init(struct stf_vin2_dev *vin_dev)
 
 static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 {
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
-#ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_C].rstc);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_P].rstc);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rstc);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rstc);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rstc);
-#else
-       reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-               RST_U0_ISPV2_TOP_WRAPPER_RST_P);
-       reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-               RST_U0_ISPV2_TOP_WRAPPER_RST_C);
-       reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
-               RSTN_U0_VIN_RST_N_PCLK
-               | RSTN_U0_VIN_RST_P_AXIRD
-               | RSTN_U0_VIN_RST_N_SYS_CLK);
-       reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, RSTN_U0_VIN_RST_P_AXIWR);
-#endif
-       reg_set_bit(vin->clkgen_base, CLK_DOM4_APB_FUNC, CLK_MUX_SEL, 0x8);
-       reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, CLK_U0_VIN_PCLK_ICG, 0x1<<31);
-       reg_set_bit(vin->clkgen_base, CLK_U0_VIN_SYS_CLK, CLK_MUX_SEL, 0x2);
-       reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, CLK_U0_ISPV2_CLK_ICG, 0x1<<31);
+       struct stfcamss *stfcamss = vin_dev->stfcamss;
 
-       reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, CLK_U0_ISPV2_MUX_SEL, 0x0);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_WRAPPER_C].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_WRAPPER_P].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PCLK].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
 
-       reg_set_bit(vin->clkgen_base, CLK_DVP_INV, CLK_POLARITY, 0x0);
-       reg_set_bit(vin->clkgen_base, CLK_U0_ISPV2_TOP_WRAPPER_CLK_C, CLK_U0_ISPV2_MUX_SEL, 0x1<<24);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PCLK].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk);
 
-       reg_set_bit(vin->clkgen_base,   CLK_U0_VIN_CLK_P_AXIWR, CLK_U0_VIN_MUX_SEL, 0x0);
+#ifdef HWBOARD_FPGA
+       clk_set_rate(stfcamss->sys_clk[STFCLK_APB_FUNC].clk, 51200000);
+       clk_set_rate(stfcamss->sys_clk[STFCLK_SYS_CLK].clk, 307200000);
+#else
+       reg_set_bit(vin->clkgen_base, CLK_DOM4_APB_FUNC, CLK_MUX_SEL, 0x8);
+       reg_set_bit(vin->clkgen_base, CLK_U0_VIN_SYS_CLK, CLK_MUX_SEL, 0x2);
+#endif
 
-       reg_set_bit(vin->clkgen_base,   CLK_U0_VIN_CLK_P_AXIWR, CLK_U0_VIN_MUX_SEL, 0x1<<24);
+       clk_set_phase(stfcamss->sys_clk[STFCLK_DVP_INV].clk, 0);
+       clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
+               stfcamss->sys_clk[STFCLK_DVP_INV].clk);
+       clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
+               stfcamss->sys_clk[STFCLK_DVP_INV].clk);
 
        return 0;
 }
@@ -147,23 +137,15 @@ static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 
 static int stf_vin_clk_disable(struct stf_vin2_dev *vin_dev)
 {
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
+       struct stfcamss *stfcamss = vin_dev->stfcamss;
 
-#ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rstc);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rstc);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rstc);
-#else
-       reg_assert_rst(vin->clkgen_base,SOFTWARE_RESET_ASSERT0_ASSERT_SET,
-               SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, RSTN_U0_VIN_RST_N_PCLK
-               | RSTN_U0_VIN_RST_N_SYS_CLK
-               | RSTN_U0_VIN_RST_P_AXIRD
-               | RSTN_U0_VIN_RST_P_AXIWR);
-#endif
+       reset_control_assert(stfcamss->sys_rst[STFRST_PCLK].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
 
-       reg_set_bit(vin->clkgen_base, CLK_U0_VIN_PCLK, CLK_U0_VIN_PCLK_ICG, 0x0);
+       clk_disable_unprepare(stfcamss->sys_clk[STFCLK_PCLK].clk);
 
        return 0;
 }
@@ -177,7 +159,6 @@ static int stf_vin_config_set(struct stf_vin2_dev *vin_dev)
 
 static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
 {
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
        print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);
@@ -198,8 +179,6 @@ static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
 static void stf_vin_wr_irq_enable(struct stf_vin2_dev *vin_dev,
                int enable)
 {
-
-
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
        unsigned int value = 0;
 
@@ -221,60 +200,6 @@ static void stf_vin_wr_irq_enable(struct stf_vin2_dev *vin_dev,
                        U0_VIN_CNFG_AXIWR0_MASK, 
                        value);
        }
-
-}
-
-static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,     int enable)
-{
-       struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
-       u32 reg = 0;
-       
-       if(enable){
-               reg_write(vin->pmu_test, SW_DEST_POWER_ON, (0x1<<5));
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0xff);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0x05);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0x50);
-
-#ifdef CONFIG_CLK_STARFIVE_JH7110
-               clk_prepare_enable(vin_dev->stfcamss->sys_clk[STFCLK_ISPCORE_2X].clk);
-               clk_prepare_enable(vin_dev->stfcamss->sys_clk[STFCLK_ISP_AXI].clk);
-#else
-               reg_set_highest_bit(vin->sys_crg, 0xCCU);
-               reg_set_highest_bit(vin->sys_crg, 0xD0U);
-#endif
-
-#ifdef CONFIG_RESET_STARFIVE_JH7110
-               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
-               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
-#else
-               reg_clear_rst(vin->sys_crg, 0x2FCU, 0x30CU, (0x1 << 9));
-               reg_clear_rst(vin->sys_crg, 0x2FCU, 0x30CU, (0x1 << 10));
-#endif
-
-       } else {
-
-#ifdef CONFIG_RESET_STARFIVE_JH7110
-               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
-               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
-#else
-               reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(9));
-               reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(10));
-#endif
-
-#ifdef CONFIG_CLK_STARFIVE_JH7110
-               clk_disable_unprepare(vin_dev->stfcamss->sys_clk[STFCLK_ISPCORE_2X].clk);
-               clk_disable_unprepare(vin_dev->stfcamss->sys_clk[STFCLK_ISP_AXI].clk);
-#else
-               reg_set_bit(vin->sys_crg, 0xccu, BIT(31), 0x0);
-               reg_set_bit(vin->sys_crg, 0xd0u, BIT(31), 0x0);
-#endif
-
-               reg_write(vin->pmu_test, SW_DEST_POWER_ON, (0x1<<5));
-               //reg_write(vin->pmu_test, SW_DEST_POWER_OFF, (0x1<<5));        //changhuang modify 01-12
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0xff);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0x0a);
-               reg_write(vin->pmu_test, SW_ENCOURAGE, 0xa0);
-       }
 }
 
 static void stf_vin_wr_rd_set_addr(struct stf_vin2_dev *vin_dev,
@@ -373,7 +298,6 @@ struct vin_hw_ops vin_ops = {
        .vin_config_set        = stf_vin_config_set,
        .vin_wr_stream_set     = stf_vin_wr_stream_set,
        .vin_wr_irq_enable     = stf_vin_wr_irq_enable,
-       .vin_power_on              = stf_vin_power_on,
        .wr_rd_set_addr        = stf_vin_wr_rd_set_addr,
        .vin_wr_set_ping_addr  = stf_vin_wr_set_ping_addr,
        .vin_wr_set_pong_addr  = stf_vin_wr_set_pong_addr,

diff --git a/drivers/media/platform/starfive/v4l2_driver/stfcamss.c b/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
index e745e2d..431e532 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stfcamss.c
@@ -56,13 +56,20 @@ static const struct reg_name mem_reg_name[] = {
 };
 
 static struct clk_bulk_data stfcamss_clocks[] = {
-       { .id = "clk_ispcore_2x" },
-       { .id = "clk_isp_axi" },
+       { .id = "clk_apb_func" },
+       { .id = "clk_pclk" },
+       { .id = "clk_sys_clk" },
+       { .id = "clk_wrapper_clk_c" },
+       { .id = "clk_dvp_inv" },
+       { .id = "clk_axiwr" },
+       { .id = "clk_mipi_rx0_pxl" },
+       { .id = "clk_pixel_clk_if0" },
+       { .id = "clk_pixel_clk_if1" },
+       { .id = "clk_pixel_clk_if2" },
+       { .id = "clk_pixel_clk_if3" },
 };
 
 static struct reset_control_bulk_data stfcamss_resets[] = {
-       { .id = "rst_isp_top_n" },
-       { .id = "rst_isp_top_axi" },
        { .id = "rst_wrapper_p" },
        { .id = "rst_wrapper_c" },
        { .id = "rst_pclk" },
@@ -1034,24 +1041,24 @@ static int stfcamss_probe(struct platform_device *pdev)
                goto err_cam;
        }
 
-#ifdef CONFIG_CLK_STARFIVE_JH7110
        stfcamss->nclks = ARRAY_SIZE(stfcamss_clocks);
        stfcamss->sys_clk = stfcamss_clocks;
 
        ret = devm_clk_bulk_get(dev, stfcamss->nclks, stfcamss->sys_clk);
-       if (ret)
+       if (ret) {
                st_err(ST_CAMSS, "faied to get clk controls\n");
-#endif
+               return ret;
+       }
 
-#ifdef CONFIG_RESET_STARFIVE_JH7110
        stfcamss->nrsts = ARRAY_SIZE(stfcamss_resets);
        stfcamss->sys_rst = stfcamss_resets;
 
        ret = devm_reset_control_bulk_get_exclusive(dev, stfcamss->nrsts,
                stfcamss->sys_rst);
-       if (ret)
+       if (ret) {
                st_err(ST_CAMSS, "faied to get reset controls\n");
-#endif
+               return ret;
+       }
 
        ret = stfcamss_get_mem_res(pdev, vin);
        if (ret) {

diff --git a/drivers/media/platform/starfive/v4l2_driver/stfcamss.h b/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
index 39dd310..5407566 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stfcamss.h
@@ -42,15 +42,22 @@ enum port_num {
 };
 
 enum stf_clk_num {
-       STFCLK_ISPCORE_2X = 0,
-       STFCLK_ISP_AXI,
+       STFCLK_APB_FUNC = 0,
+       STFCLK_PCLK,
+       STFCLK_SYS_CLK,
+       STFCLK_WRAPPER_CLK_C,
+       STFCLK_DVP_INV,
+       STFCLK_AXIWR,
+       STFCLK_MIPI_RX0_PXL,
+       STFCLK_PIXEL_CLK_IF0,
+       STFCLK_PIXEL_CLK_IF1,
+       STFCLK_PIXEL_CLK_IF2,
+       STFCLK_PIXEL_CLK_IF3,
        STFCLK_NUM
 };
 
 enum stf_rst_num {
-       STFRST_ISP_TOP_N = 0,
-       STFRST_ISP_TOP_AXI,
-       STFRST_WRAPPER_P,
+       STFRST_WRAPPER_P = 0,
        STFRST_WRAPPER_C,
        STFRST_PCLK,
        STFRST_SYS_CLK,
@@ -63,16 +70,6 @@ enum stf_rst_num {
        STFRST_NUM
 };
 
-struct stfcamss_clk {
-       struct clk *clk;
-       const char *name;
-};
-
-struct stfcamss_rst {
-       struct reset_control *rst;
-       const char *name;
-};
-
 struct stfcamss {
        struct stf_vin_dev *vin;  // stfcamss phy res
        struct v4l2_device v4l2_dev;