soc: mediatek: pm-domains: Fix the power glitch issue

Power reset maybe generate unexpected signal. In order to avoid
the glitch issue, we need to enable isolation first to guarantee the
stable signal when power reset is triggered.

Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221014102029.1162-1-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 09e3c38b8466434b5dfd9eb732494e028670c59d..474b272f9b02d6cf305f59bf238762d9db93827d 100644 (file)
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
        clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
 
        /* subsys power off */
-       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
        regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
        regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
+       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
        regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
        regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);