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fixed to test feature, not CPU
author
Sanjay Patel
<spatel@rotateright.com>
Fri, 6 Mar 2015 20:51:25 +0000
(20:51 +0000)
committer
Sanjay Patel
<spatel@rotateright.com>
Fri, 6 Mar 2015 20:51:25 +0000
(20:51 +0000)
llvm-svn: 231513
llvm/test/CodeGen/X86/fnabs.ll
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diff --git
a/llvm/test/CodeGen/X86/fnabs.ll
b/llvm/test/CodeGen/X86/fnabs.ll
index
19718d3
..
a3ddfb9
100644
(file)
--- a/
llvm/test/CodeGen/X86/fnabs.ll
+++ b/
llvm/test/CodeGen/X86/fnabs.ll
@@
-1,4
+1,4
@@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -m
cpu=corei7-
avx| FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -m
attr=
avx| FileCheck %s
; Verify that we generate a single OR instruction for a scalar, vec128, and vec256
; FNABS(x) operation -> FNEG (FABS(x)).