fixed to test feature, not CPU

llvm-svn: 231513

diff --git a/llvm/test/CodeGen/X86/fnabs.ll b/llvm/test/CodeGen/X86/fnabs.ll
index 19718d3..a3ddfb9 100644 (file)
--- a/llvm/test/CodeGen/X86/fnabs.ll
+++ b/llvm/test/CodeGen/X86/fnabs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx| FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx| FileCheck %s
 
 ; Verify that we generate a single OR instruction for a scalar, vec128, and vec256
 ; FNABS(x) operation -> FNEG (FABS(x)).