compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x1>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x2>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x3>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
- entry-latency-us = <5000>;
+ entry-latency-us = <4000>;
exit-latency-us = <5000>;
- min-residency-us = <15000>;
+ min-residency-us = <10000>;
};
};
};
safe_svcmode_maskall r1
mov r1, #0
ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
+ ALT_SMP(and r2, r0, #1<<24)
+ ALT_SMP(cmp r2, #0)
+ ALT_SMP(beq 2f)
+ ALT_SMP(lsr r0, r0, #8)
ALT_UP_B(1f)
+2:
adr r2, mpidr_hash_ptr
ldr r3, [r2]
add r2, r2, r3 @ r2 = struct mpidr_hash phys address
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
-// cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
- entry-latency-us = <5000>;
+ entry-latency-us = <4000>;
exit-latency-us = <5000>;
- min-residency-us = <15000>;
+ min-residency-us = <10000>;
};
};
};
/* find the mpidr_hash */
ldr_l x1, sleep_save_stash
mrs x7, mpidr_el1
+ ubfx x2, x7, #24, 1
+ cbz x2, __cpu_suspend_enter_cont
+ lsr x7, x7, #8
+__cpu_suspend_enter_cont:
adr_l x9, mpidr_hash
ldr x10, [x9, #MPIDR_HASH_MASK]
/*
ENTRY(_cpu_resume)
mrs x1, mpidr_el1
+ ubfx x2, x1, #24, 1
+ cbz x2, _cpu_resume_cont
+ lsr x1, x1, #8
+_cpu_resume_cont:
adr_l x8, mpidr_hash // x8 = struct mpidr_hash virt address
/* retrieve mpidr_hash members to compute the hash */