Revert "[lldb] Set return status to failed when adding a command error"

This reverts commit e05b03cf4f45ac5ee63c59a3464e7d484884645c.

While I investigate a register test failure:
http://green.lab.llvm.org/green/blue/organizations/jenkins/lldb-cmake/detail/lldb-cmake/32693/pipeline/

diff --git a/lldb/source/Interpreter/CommandReturnObject.cpp b/lldb/source/Interpreter/CommandReturnObject.cpp
index 531c1f2..c3f32a4 100644 (file)
--- a/lldb/source/Interpreter/CommandReturnObject.cpp
+++ b/lldb/source/Interpreter/CommandReturnObject.cpp
@@ -44,8 +44,6 @@ CommandReturnObject::CommandReturnObject(bool colors)
     : m_out_stream(colors), m_err_stream(colors) {}
 
 void CommandReturnObject::AppendErrorWithFormat(const char *format, ...) {
-  SetStatus(eReturnStatusFailed);
-
   if (!format)
     return;
   va_list args;
@@ -100,7 +98,6 @@ void CommandReturnObject::AppendWarning(llvm::StringRef in_string) {
 void CommandReturnObject::AppendError(llvm::StringRef in_string) {
   if (in_string.empty())
     return;
-  SetStatus(eReturnStatusFailed);
   error(GetErrorStream()) << in_string.rtrim() << '\n';
 }
 
@@ -117,6 +114,7 @@ void CommandReturnObject::SetError(llvm::StringRef error_str) {
     return;
 
   AppendError(error_str);
+  SetStatus(eReturnStatusFailed);
 }
 
 // Similar to AppendError, but do not prepend 'Status: ' to message, and don't
@@ -126,7 +124,6 @@ void CommandReturnObject::AppendRawError(llvm::StringRef in_string) {
   if (in_string.empty())
     return;
   GetErrorStream() << in_string;
-  SetStatus(eReturnStatusFailed);
 }
 
 void CommandReturnObject::SetStatus(ReturnStatus status) { m_status = status; }

diff --git a/lldb/test/API/commands/register/register/register_command/TestRegisters.py b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
index 7acf3a4..5ec46c1 100644 (file)
--- a/lldb/test/API/commands/register/register/register_command/TestRegisters.py
+++ b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
@@ -41,18 +41,13 @@ class RegisterCommandsTestCase(TestBase):
         self.expect("register read -a", MISSING_EXPECTED_REGISTERS,
                     substrs=['registers were unavailable'], matching=False)
 
-        all_registers = self.res.GetOutput()
-
         if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
             self.runCmd("register read xmm0")
-            if "ymm15 = " in all_registers:
-              self.runCmd("register read ymm15")  # may be available
-            if "bnd0 = " in all_registers:
-              self.runCmd("register read bnd0")  # may be available
+            self.runCmd("register read ymm15")  # may be available
+            self.runCmd("register read bnd0")  # may be available
         elif self.getArchitecture() in ['arm', 'armv7', 'armv7k', 'arm64', 'arm64e', 'arm64_32']:
             self.runCmd("register read s0")
-            if "q15 = " in all_registers:
-              self.runCmd("register read q15")  # may be available
+            self.runCmd("register read q15")  # may be available
 
         self.expect(
             "register read -s 4",
@@ -418,8 +413,7 @@ class RegisterCommandsTestCase(TestBase):
                 self.write_and_read(currentFrame, "ymm7", new_value)
                 self.expect("expr $ymm0", substrs=['vector_type'])
             else:
-                self.expect("register read ymm0", substrs=["Invalid register name 'ymm0'"],
-                            error=True)
+                self.runCmd("register read ymm0")
 
             if has_mpx:
                 # Test write and read for bnd0.
@@ -434,8 +428,7 @@ class RegisterCommandsTestCase(TestBase):
                 self.write_and_read(currentFrame, "bndstatus", new_value)
                 self.expect("expr $bndstatus", substrs = ['vector_type'])
             else:
-                self.expect("register read bnd0", substrs=["Invalid register name 'bnd0'"],
-                            error=True)
+                self.runCmd("register read bnd0")
 
     def convenience_registers(self):
         """Test convenience registers."""
@@ -457,7 +450,7 @@ class RegisterCommandsTestCase(TestBase):
         # Now write rax with a unique bit pattern and test that eax indeed
         # represents the lower half of rax.
         self.runCmd("register write rax 0x1234567887654321")
-        self.expect("register read rax",
+        self.expect("register read rax 0x1234567887654321",
                     substrs=['0x1234567887654321'])
 
     def convenience_registers_with_process_attach(self, test_16bit_regs):

diff --git a/lldb/test/Shell/Commands/command-backtrace-parser-1.test b/lldb/test/Shell/Commands/command-backtrace-parser-1.test
deleted file mode 100644 (file)
index 339c666..0000000
--- a/lldb/test/Shell/Commands/command-backtrace-parser-1.test
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: %lldb -s %s 2>&1 | FileCheck %s
-
-# Make sure this is not rejected by the parser as invalid syntax.
-# Blank characters after the '1' are important, as we're testing the parser.
-bt 1      
-# CHECK: error: invalid target

diff --git a/lldb/test/Shell/Commands/command-backtrace-parser-2.test b/lldb/test/Shell/Commands/command-backtrace.test
similarity index 50%
rename from lldb/test/Shell/Commands/command-backtrace-parser-2.test
rename to lldb/test/Shell/Commands/command-backtrace.test
index 5f91cf3..2816f5f 100644 (file)
--- a/lldb/test/Shell/Commands/command-backtrace-parser-2.test
+++ b/lldb/test/Shell/Commands/command-backtrace.test
@@ -1,6 +1,12 @@
+# Check basic functionality of command bt.
 # RUN: %lldb -s %s 2>&1 | FileCheck %s
 
 # Make sure this is not rejected by the parser as invalid syntax.
+# Blank characters after the '1' are important, as we're testing the parser.
+bt 1      
+# CHECK: error: invalid target
+
+# Make sure this is not rejected by the parser as invalid syntax.
 # Blank characters after the 'all' are important, as we're testing the parser.
 bt all       
 # CHECK: error: invalid target