#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
#include "gt/intel_gt.h"
+ #include "gt/intel_gt_regs.h"
-static int init_fake_lmem_bar(struct intel_memory_region *mem)
-{
- struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
- unsigned long n;
- int ret;
-
- /* We want to 1:1 map the mappable aperture to our reserved region */
-
- mem->fake_mappable.start = 0;
- mem->fake_mappable.size = resource_size(&mem->region);
- mem->fake_mappable.color = I915_COLOR_UNEVICTABLE;
-
- ret = drm_mm_reserve_node(&ggtt->vm.mm, &mem->fake_mappable);
- if (ret)
- return ret;
-
- mem->remap_addr = dma_map_resource(i915->drm.dev,
- mem->region.start,
- mem->fake_mappable.size,
- DMA_BIDIRECTIONAL,
- DMA_ATTR_FORCE_CONTIGUOUS);
- if (dma_mapping_error(i915->drm.dev, mem->remap_addr)) {
- drm_mm_remove_node(&mem->fake_mappable);
- return -EINVAL;
- }
-
- for (n = 0; n < mem->fake_mappable.size >> PAGE_SHIFT; ++n) {
- ggtt->vm.insert_page(&ggtt->vm,
- mem->remap_addr + (n << PAGE_SHIFT),
- n << PAGE_SHIFT,
- I915_CACHE_NONE, 0);
- }
-
- mem->region = (struct resource)DEFINE_RES_MEM(mem->remap_addr,
- mem->fake_mappable.size);
-
- return 0;
-}
-
-static void release_fake_lmem_bar(struct intel_memory_region *mem)
-{
- if (!drm_mm_node_allocated(&mem->fake_mappable))
- return;
-
- drm_mm_remove_node(&mem->fake_mappable);
-
- dma_unmap_resource(mem->i915->drm.dev,
- mem->remap_addr,
- mem->fake_mappable.size,
- DMA_BIDIRECTIONAL,
- DMA_ATTR_FORCE_CONTIGUOUS);
-}
-
static int
region_lmem_release(struct intel_memory_region *mem)
{
* Copyright © 2021 Intel Corporation
*/
+ #include <drm/drm_cache.h>
+
#include "i915_drv.h"
+ #include "i915_reg.h"
#include "intel_guc_slpc.h"
+ #include "intel_mchbar_regs.h"
#include "gt/intel_gt.h"
+ #include "gt/intel_gt_regs.h"
+#include "gt/intel_rps.h"
static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
{
#define SGGI_DIS REG_BIT(15)
#define SGR_DIS REG_BIT(13)
+#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
+#define XEHPSDV_CCS_BASE_SHIFT 8
+
+/* gamt regs */
+#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
+#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
+#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
+
+#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
+#define MMCD_PCLA (1 << 31)
+#define MMCD_HOTSPOT_EN (1 << 27)
+
#define _ICL_PHY_MISC_A 0x64C00
#define _ICL_PHY_MISC_B 0x64C04
- #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
- _ICL_PHY_MISC_B)
+ #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+ #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+ #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+ ICL_PHY_MISC(port))
#define ICL_PHY_MISC_MUX_DDID (1 << 28)
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
INTEL_ICL_PORT_F_IDS(0),
};
+static const u16 subplatform_uy_ids[] = {
+ INTEL_TGL_12_GT2_IDS(0),
+};
+
+ static const u16 subplatform_n_ids[] = {
+ INTEL_ADLN_IDS(0),
+ };
+
static const u16 subplatform_rpls_ids[] = {
INTEL_RPLS_IDS(0),
};
} else if (find_devid(devid, subplatform_portf_ids,
ARRAY_SIZE(subplatform_portf_ids))) {
mask = BIT(INTEL_SUBPLATFORM_PORTF);
+ } else if (find_devid(devid, subplatform_uy_ids,
+ ARRAY_SIZE(subplatform_uy_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_UY);
+ } else if (find_devid(devid, subplatform_n_ids,
+ ARRAY_SIZE(subplatform_n_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_N);
} else if (find_devid(devid, subplatform_rpls_ids,
ARRAY_SIZE(subplatform_rpls_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL_S);
#include <linux/prime_numbers.h>
#include "gem/i915_gem_context.h"
+ #include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_region.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"