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AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 8 Jan 2020 19:12:19 +0000 (14:12 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Thu, 9 Jan 2020 15:29:31 +0000 (10:29 -0500)
Reduces diff for a future patch.

llvm/lib/Target/AMDGPU/DSInstructions.td patch | blob | history

diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index f008b80..f0987cf 100644 (file)
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -619,7 +619,7 @@ def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
 
 def : GCNPat <
   (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
-  (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
+  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16imm $offset16), (i1 0))
 >;
 
 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
Domain: System / Toolchain;