break;
case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
--- - /*
--- - * I2S format, CODEC supplies BCLK and LRC clocks.
--- - *
--- - * The SSC transmit clock is obtained from the BCLK signal on
--- - * on the TK line, and the SSC receive clock is
--- - * generated from the transmit clock.
-- - *
-- - * For single channel data, one sample is transferred
-- - * on the falling edge of the LRC clock.
-- - * For two channel data, one sample is
-- - * transferred on both edges of the LRC clock.
--- - */
-- - start_event = ((channels == 1)
-- - ? SSC_START_FALLING_RF
-- - : SSC_START_EDGE_RF);
-- -
+++ + /* I2S format, CODEC supplies BCLK and LRC clocks. */
rcmr = SSC_BF(RCMR_PERIOD, 0)
| SSC_BF(RCMR_STTDLY, START_DELAY)
-- - | SSC_BF(RCMR_START, start_event)
++ + | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
| SSC_BF(TFMR_FSDEN, 0)
| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
| SSC_BF(TFMR_FSLEN, 0)
-- - | SSC_BF(TFMR_DATNB, 0)
++ + | SSC_BF(TFMR_DATNB, (channels - 1))
++ + | SSC_BIT(TFMR_MSBF)
++ + | SSC_BF(TFMR_DATDEF, 0)
++ + | SSC_BF(TFMR_DATLEN, (bits - 1));
++ + break;
++ +
+++ + case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
+++ + /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
+++ + if (bits > 16 && !ssc->pdata->has_fslen_ext) {
+++ + dev_err(dai->dev,
+++ + "sample size %d is too large for SSC device\n",
+++ + bits);
+++ + return -EINVAL;
+++ + }
+++ +
+++ + fslen_ext = (bits - 1) / 16;
+++ + fslen = (bits - 1) % 16;
+++ +
+++ + rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
+++ + | SSC_BF(RCMR_STTDLY, START_DELAY)
+++ + | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
+++ + | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
+++ + | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
+++ + | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
+++ + SSC_CKS_PIN : SSC_CKS_CLOCK);
+++ +
+++ + rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
+++ + | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
+++ + | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
+++ + | SSC_BF(RFMR_FSLEN, fslen)
+++ + | SSC_BF(RFMR_DATNB, (channels - 1))
+++ + | SSC_BIT(RFMR_MSBF)
+++ + | SSC_BF(RFMR_LOOP, 0)
+++ + | SSC_BF(RFMR_DATLEN, (bits - 1));
+++ +
+++ + tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
+++ + | SSC_BF(TCMR_STTDLY, START_DELAY)
+++ + | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
+++ + | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
+++ + | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
+++ + | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
+++ + SSC_CKS_CLOCK : SSC_CKS_PIN);
+++ +
+++ + tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
+++ + | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
+++ + | SSC_BF(TFMR_FSDEN, 0)
+++ + | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
+++ + | SSC_BF(TFMR_FSLEN, fslen)
+++ + | SSC_BF(TFMR_DATNB, (channels - 1))
+ | SSC_BIT(TFMR_MSBF)
+ | SSC_BF(TFMR_DATDEF, 0)
+ | SSC_BF(TFMR_DATLEN, (bits - 1));
+ break;
+
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
/*
* DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.