riscv: Implement semihost.h for earlycon semihost driver

Per RISC-V semihosting spec [1], implement semihost.h for the existing
Arm semihosting earlycon driver to work on RISC-V.

Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221209150437.795918-3-bmeng@tinylab.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h
new file mode 100644 (file)
index 0000000..557a349
--- /dev/null
+++ b/arch/riscv/include/asm/semihost.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
+ */
+
+#ifndef _RISCV_SEMIHOST_H_
+#define _RISCV_SEMIHOST_H_
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+       asm volatile("addi    a1, %0, 0\n"
+                    "addi    a0, zero, 3\n"
+                    ".balign 16\n"
+                    ".option push\n"
+                    ".option norvc\n"
+                    "slli    zero, zero, 0x1f\n"
+                    "ebreak\n"
+                    "srai    zero, zero, 0x7\n"
+                    ".option pop\n"
+                    : : "r" (&c) : "a0", "a1", "memory");
+}
+
+#endif /* _RISCV_SEMIHOST_H_ */

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index c55b947..5a2cf96 100644 (file)
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE
 
 config SERIAL_EARLYCON_ARM_SEMIHOST
        bool "Early console using ARM semihosting"
-       depends on ARM64 || ARM
+       depends on ARM64 || ARM || RISCV
        select SERIAL_CORE
        select SERIAL_CORE_CONSOLE
        select SERIAL_EARLYCON