2010-09-17 Tejas Belagod <tejas.belagod@arm.com>

	* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
	of just RR.

2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>

	* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
	* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv.  Also
	add disassembly for test added in copro.s

2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>

	* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f8fb4f4..a2bac57 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
+       of just RR.
+
 2010-09-17  Andrew Burgess  <aburgess@broadcom.com>
 
        PR gas/12011

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f1ffe9c..cebf2df 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -16704,7 +16704,7 @@ static const struct asm_opcode insns[] =
  TCE("stc",    c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),             lstc,   lstc),
  TC3("stcl",   c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),             lstc,   lstc),
  TCE("mcr",    e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
- TCE("mrc",    e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
+ TCE("mrc",    e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b),   co_reg, co_reg),
 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & arm_ext_v2s /* ARM 3 - swp instructions.  */

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2bd1bec..cd5f25c 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
+       * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv.  Also
+       add disassembly for test added in copro.s
+
 2010-09-17  Andrew Burgess  <aburgess@broadcom.com>
 
        PR gas/12011

diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
index e041270..d007c81 100644 (file)
--- a/gas/testsuite/gas/arm/copro.d
+++ b/gas/testsuite/gas/arm/copro.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
 0+028 <[^>]*> 3ca4860c         stccc   6, cr8, \[r4\], #48.*
 0+02c <[^>]*> ed0f7101         stfs    f7, \[pc, #-4\] ; .* <bar>
 0+030 <[^>]*> ee715212         mrc     2, 3, r5, cr1, cr2, \{0\}
-0+034 <[^>]*> aeb1f4f2         mrcge   4, 5, pc, cr1, cr2, \{7\}
+0+034 <[^>]*> aeb1f4f2         mrcge   4, 5, APSR_nzcv, cr1, cr2, \{7\}
 0+038 <[^>]*> ee215711         mcr     7, 1, r5, cr1, cr1, \{0\}
 0+03c <[^>]*> be228519         mcrlt   5, 1, r8, cr2, cr9, \{0\}
 0+040 <[^>]*> ec907300         ldc     3, cr7, \[r0\], \{0\}
@@ -39,3 +39,4 @@ Disassembly of section .text:
 0+074 <[^>]*> ec407efe         mcrr    14, 15, r7, r0, cr14
 0+078 <[^>]*> e1a00000         nop                     ; \(mov r0, r0\)
 0+07c <[^>]*> e1a00000         nop                     ; \(mov r0, r0\)
+0+080 <[^>]*> aeb1f4f2         mrcge   4, 5, APSR_nzcv, cr1, cr2, \{7\}

diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s
index b9ef056..0ed0e05 100644 (file)
--- a/gas/testsuite/gas/arm/copro.s
+++ b/gas/testsuite/gas/arm/copro.s
@@ -44,3 +44,6 @@ bar:
        # Extra instructions to allow for code alignment in arm-aout target.
        nop
        nop
+
+       # UAL-syntax for MRC with APSR. Pre-UAL was PC
+       mrcge   p4, 5, APSR_nzcv, cr1, cr2, 7

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 992a740..f7d0f53 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
+
 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b16d50f..831b26c 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -474,6 +474,7 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
   {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+  {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},