c,
ctrl->channels[c].regs[R_MASKED_INTR]));
- if (ctrl->channels[c].regs[R_MASKED_INTR])
- qemu_irq_raise(ctrl->channels[c].irq[0]);
- else
- qemu_irq_lower(ctrl->channels[c].irq[0]);
+ qemu_set_irq(ctrl->channels[c].irq[0],
+ !!ctrl->channels[c].regs[R_MASKED_INTR]);
}
static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
static void ser_update_irq(struct etrax_serial_t *s)
{
- uint32_t o_irq = s->r_masked_intr;
-
s->r_intr &= ~(s->rw_ack_intr);
s->r_masked_intr = s->r_intr & s->rw_intr_mask;
- if (o_irq != s->r_masked_intr) {
- D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
- s->rw_intr_mask, s->r_intr,
- s->r_masked_intr, s->rw_ack_intr));
- if (s->r_masked_intr)
- qemu_irq_raise(s->irq[0]);
- else
- qemu_irq_lower(s->irq[0]);
- }
+ D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
+ s->rw_intr_mask, s->r_intr,
+ s->r_masked_intr, s->rw_ack_intr));
+ qemu_set_irq(s->irq[0], !!s->r_masked_intr);
s->rw_ack_intr = 0;
}
-
static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
{
D(CPUState *env = opaque);
t->r_masked_intr = t->r_intr & t->rw_intr_mask;
D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
- if (t->r_masked_intr)
- qemu_irq_raise(t->irq[0]);
- else
- qemu_irq_lower(t->irq[0]);
+ qemu_set_irq(t->irq[0], !!t->r_masked_intr);
}
static void timer0_hit(void *opaque)