rockchip: Kconfig: Enable SPL support for rk3568
authorNico Cheng <nico.cheng@rock-chips.com>
Tue, 26 Oct 2021 02:42:19 +0000 (10:42 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Fri, 24 Dec 2021 03:10:24 +0000 (11:10 +0800)
Enable SPL support in Kconfig and add some related option in
rk3568_common.h

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/Kconfig
configs/evb-rk3568_defconfig
include/configs/rk3568_common.h

index da6871e..d840c59 100644 (file)
@@ -261,6 +261,8 @@ config ROCKCHIP_RK3399
 config ROCKCHIP_RK3568
        bool "Support Rockchip RK3568"
        select ARM64
+       select SUPPORT_SPL
+       select SPL
        select CLK
        select PINCTRL
        select RAM
index 7453ccf..17664e1 100644 (file)
@@ -2,21 +2,43 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -30,6 +52,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
index afe5050..25d7c5c 100644 (file)
 #define CONFIG_IRAM_BASE               0xfdcc0000
 
 #define CONFIG_SYS_INIT_SP_ADDR                0x00c00000
+
+#define CONFIG_SPL_STACK               0x00400000
+#define CONFIG_SPL_MAX_SIZE            0x20000
+#define CONFIG_SPL_BSS_START_ADDR      0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x4000
+
 #define CONFIG_SYS_BOOTM_LEN           (64 << 20)      /* 64M */
 
 #define CONFIG_SYS_SDRAM_BASE          0