arm64: dts: imx8mp: Add CSIS DT nodes

Add DT nodes for the two CSI-2 receivers of the i.MX8MP.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index f813919..5a0424a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1342,6 +1342,66 @@
                                };
                        };
 
+                       mipi_csi_0: csi@32e40000 {
+                               compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+                               reg = <0x32e40000 0x10000>;
+                               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               clock-frequency = <500000000>;
+                               clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+                               clock-names = "pclk", "wrap", "phy", "axi";
+                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+                               assigned-clock-rates = <500000000>;
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                       };
+                               };
+                       };
+
+                       mipi_csi_1: csi@32e50000 {
+                               compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+                               reg = <0x32e50000 0x10000>;
+                               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                               clock-frequency = <266000000>;
+                               clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+                               clock-names = "pclk", "wrap", "phy", "axi";
+                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+                               assigned-clock-rates = <266000000>;
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                       };
+                               };
+                       };
+
                        pcie_phy: pcie-phy@32f00000 {
                                compatible = "fsl,imx8mp-pcie-phy";
                                reg = <0x32f00000 0x10000>;