/// \return The size of a cache line in bytes.
unsigned getCacheLineSize() const;
+ /// \return How much before a load we should place the prefetch instruction.
+ /// This is currently measured in number of instructions.
+ unsigned getPrefetchDistance() const;
+
/// \return The maximum interleave factor that any transform should try to
/// perform for this target. This number depends on the level of parallelism
/// and the number of execution units in the CPU.
virtual unsigned getNumberOfRegisters(bool Vector) = 0;
virtual unsigned getRegisterBitWidth(bool Vector) = 0;
virtual unsigned getCacheLineSize() = 0;
+ virtual unsigned getPrefetchDistance() = 0;
virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
virtual unsigned
getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
unsigned getCacheLineSize() override {
return Impl.getCacheLineSize();
}
+ unsigned getPrefetchDistance() override { return Impl.getPrefetchDistance(); }
unsigned getMaxInterleaveFactor(unsigned VF) override {
return Impl.getMaxInterleaveFactor(VF);
}
unsigned getCacheLineSize() { return 0; }
+ unsigned getPrefetchDistance() { return 0; }
+
unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
return TTIImpl->getCacheLineSize();
}
+unsigned TargetTransformInfo::getPrefetchDistance() const {
+ return TTIImpl->getPrefetchDistance();
+}
+
unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
return TTIImpl->getMaxInterleaveFactor(VF);
}
PrefetchWrites("ppc-loop-prefetch-writes", cl::Hidden, cl::init(false),
cl::desc("Prefetch write addresses"));
-// This seems like a reasonable default for the BG/Q (this pass is enabled, by
-// default, only on the BG/Q).
-static cl::opt<unsigned>
-PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
- cl::desc("The loop prefetch distance"));
-
namespace llvm {
void initializePPCLoopDataPrefetchPass(PassRegistry&);
}
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
assert(TTI->getCacheLineSize() && "Cache line size is not set for target");
+ assert(TTI->getPrefetchDistance() &&
+ "Prefetch distance is not set for target");
bool MadeChange = false;
if (!LoopSize)
LoopSize = 1;
- unsigned ItersAhead = PrefDist/LoopSize;
+ unsigned ItersAhead = TTI->getPrefetchDistance() / LoopSize;
if (!ItersAhead)
ItersAhead = 1;
CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
cl::desc("The loop prefetch cache line size"));
+// This seems like a reasonable default for the BG/Q (this pass is enabled, by
+// default, only on the BG/Q).
+static cl::opt<unsigned>
+PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
+ cl::desc("The loop prefetch distance"));
+
//===----------------------------------------------------------------------===//
//
// PPC cost model.
return CacheLineSize;
}
+unsigned PPCTTIImpl::getPrefetchDistance() { return PrefDist; }
+
unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
unsigned Directive = ST->getDarwinDirective();
// The 440 has no SIMD support, but floating-point instructions
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getCacheLineSize();
+ unsigned getPrefetchDistance();
unsigned getMaxInterleaveFactor(unsigned VF);
int getArithmeticInstrCost(
unsigned Opcode, Type *Ty,