+2009-11-25 Richard Henderson <rth@redhat.com>
+
+ * gcc.dg/vect/pr36493.c: Call check_vect.
+ * gcc.dg/vect/pr37539.c: Likewise.
+ * gcc.dg/vect/vect-nest-cycle-3.c: Call check_vect earlier.
+ * tree-vect.h (check_vect): Use cpuid for x86.
+
2009-11-25 Eric Botcazou <ebotcazou@adacore.com>
* gnat.dg/specs/pack6.ads: New test.
/* Check if system supports SIMD */
#include <signal.h>
+#if defined(__i386__) || defined(__x86_64__)
+# include "cpuid.h"
+#endif
+
extern void abort (void);
extern void exit (int);
-void
+static void
sig_ill_handler (int sig)
{
exit(0);
}
-void check_vect (void)
+static void __attribute__((noinline))
+check_vect (void)
{
signal(SIGILL, sig_ill_handler);
#if defined(__PAIRED__)
/* Altivec instruction, 'vor %v0,%v0,%v0'. */
asm volatile (".long 0x10000484");
#elif defined(__i386__) || defined(__x86_64__)
- /* SSE2 instruction: movsd %xmm0,%xmm0 */
- asm volatile (".byte 0xf2,0x0f,0x10,0xc0");
+ {
+ int a, b, c, d, want_level, want_c, want_d;
+
+ /* Determine what instruction set we've been compiled for, and detect
+ that we're running with it. This allows us to at least do a compile
+ check for, e.g. SSE4.1 when the machine only supports SSE2. */
+# ifdef __XOP__
+ want_level = 0x80000001, want_c = bit_XOP, want_d = 0;
+# elif defined(__AVX__)
+ want_level = 1, want_c = bit_AVX, want_d = 0;
+# elif defined(__SSE4_1__)
+ want_level = 1, want_c = bit_SSE4_1, want_d = 0;
+# elif defined(__SSSE3__)
+ want_level = 1, want_c = bit_SSSE3, want_d = 0;
+# else
+ want_level = 1, want_c = 0, want_d = bit_SSE2;
+# endif
+
+ if (!__get_cpuid (want_level, &a, &b, &c, &d)
+ || ((c & want_c) | (d & want_d)) == 0)
+ exit (0);
+ }
#elif defined(__sparc__)
asm volatile (".word\t0x81b007c0");
#elif defined(__arm__)