armv7: s5pc1xx: improve cache handling

Move cache handling code to C file, and add enable_caches() and
disable_caches() functions.

Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
deleted file mode 100644 (file)
index 3089592..0000000
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * based on arch/arm/cpu/armv7/omap3/cache.S
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-.align 5
-
-#include <linux/linkage.h>
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-ENTRY(v7_outer_cache_enable)
-       push    {r0, r1, r2, lr}
-       mrc     15, 0, r3, cr1, cr0, 1
-       orr     r3, r3, #2
-       mcr     15, 0, r3, cr1, cr0, 1
-       pop     {r1, r2, r3, pc}
-ENDPROC(v7_outer_cache_enable)
-
-ENTRY(v7_outer_cache_disable)
-       push    {r0, r1, r2, lr}
-       mrc     15, 0, r3, cr1, cr0, 1
-       bic     r3, r3, #2
-       mcr     15, 0, r3, cr1, cr0, 1
-       pop     {r1, r2, r3, pc}
-ENDPROC(v7_outer_cache_disable)
-#endif

diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c
new file mode 100644 (file)
index 0000000..51af299
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Robert Baldyga <r.baldyga@samsung.com>
+ *
+ * based on arch/arm/cpu/armv7/omap3/cache.S
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       dcache_enable();
+}
+
+void disable_caches(void)
+{
+       dcache_disable();
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+       __asm(
+               "push    {r0, r1, r2, lr}\n\t"
+               "mrc     15, 0, r3, cr1, cr0, 1\n\t"
+               "orr     r3, r3, #2\n\t"
+               "mcr     15, 0, r3, cr1, cr0, 1\n\t"
+               "pop     {r1, r2, r3, pc}"
+       );
+}
+
+void v7_outer_cache_disable(void)
+{
+       __asm(
+               "push    {r0, r1, r2, lr}\n\t"
+               "mrc     15, 0, r3, cr1, cr0, 1\n\t"
+               "bic     r3, r3, #2\n\t"
+               "mcr     15, 0, r3, cr1, cr0, 1\n\t"
+               "pop     {r1, r2, r3, pc}"
+       );
+}
+#endif