[AArch64] Implement <su><maxmin>v2di3 pattern

gcc/:
        PR target/63424
        * config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): New.

gcc/testsuite/:
        PR target/63424
        * gcc.target/aarch64/pr63424.c: New test.

From-SVN: r217786

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aeb8fad..d7a687a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -5,6 +5,11 @@
 
 2014-11-19  Renlin Li  <Renlin.Li@arm.com>
 
+    PR target/63424
+       * config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): New.
+
+2014-11-19  Renlin Li  <Renlin.Li@arm.com>
+
     PR middle-end/63762
        * ira.c (ira): Update preferred class.
 

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 43bfec9..2e71cb9 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -953,6 +953,39 @@
   [(set_attr "type" "neon_minmax<q>")]
 )
 
+(define_expand "<su><maxmin>v2di3"
+ [(set (match_operand:V2DI 0 "register_operand" "")
+       (MAXMIN:V2DI (match_operand:V2DI 1 "register_operand" "")
+                    (match_operand:V2DI 2 "register_operand" "")))]
+ "TARGET_SIMD"
+{
+  enum rtx_code cmp_operator;
+  rtx cmp_fmt;
+
+  switch (<CODE>)
+    {
+    case UMIN:
+      cmp_operator = LTU;
+      break;
+    case SMIN:
+      cmp_operator = LT;
+      break;
+    case UMAX:
+      cmp_operator = GTU;
+      break;
+    case SMAX:
+      cmp_operator = GT;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
+  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
+              operands[2], cmp_fmt, operands[1], operands[2]));
+  DONE;
+})
+
 ;; vec_concat gives a new vector with the low elements from operand 1, and
 ;; the high elements from operand 2.  That is to say, given op1 = { a, b }
 ;; op2 = { c, d }, vec_concat (op1, op2) = { a, b, c, d }.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f5fb9db..840a1c1 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,4 +1,8 @@
 2014-11-19  Renlin Li  <Renlin.Li@arm.com>
+    PR target/63424
+       * gcc.target/aarch64/pr63424.c: New test.
+
+2014-11-19  Renlin Li  <Renlin.Li@arm.com>
 
     PR middle-end/63762
        * gcc.dg/pr63762.c: New test. 

diff --git a/gcc/testsuite/gcc.target/aarch64/pr63424.c b/gcc/testsuite/gcc.target/aarch64/pr63424.c
new file mode 100644 (file)
index 0000000..c6bd762
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr63424.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include <stdint.h>
+
+uint32_t
+truncate_int (const unsigned long long value)
+{
+  if ( value < 0 )
+    {
+      return 0;
+    }
+  else if ( value > UINT32_MAX )
+    {
+      return UINT32_MAX;
+    }
+  else
+    return (uint32_t)value;
+}
+
+uint32_t
+mul (const unsigned long long x, const unsigned long long y)
+{
+  uint32_t value = truncate_int (x * y);
+  return value;
+}
+
+uint32_t *
+test(unsigned size, uint32_t *a, uint32_t s)
+{
+  unsigned i;
+
+  for (i = 0; i < size; i++)
+    {
+      a[i] = mul (a[i], s);
+    }
+
+  return a;
+}