Solve xHCI detect SS device as HS device issue.

BZ: 33811

This is a workaround for hardware bug. When USB3 phy in P3 state, its
RxDetect is not work well. So force PHY change to P2 state when USB3
controller want to perform receiver detection.

Change-Id: Ifbe3af1a47c784bd0afa4f5e0c20f5c228d6c161
Signed-off-by: Yu Wang <yu.y.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/46561
Reviewed-by: Tang, Richard <richard.tang@intel.com>
Tested-by: Sun, Jianhua <jianhua.sun@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/usb/otg/dwc_otg3.c b/drivers/usb/otg/dwc_otg3.c
index 898aabd..89aa360 100644 (file)
--- a/drivers/usb/otg/dwc_otg3.c
+++ b/drivers/usb/otg/dwc_otg3.c
@@ -428,7 +428,7 @@ static enum dwc_otg_state do_charger_detection(struct dwc_otg2 *otg)
 static enum dwc_otg_state do_connector_id_status(struct dwc_otg2 *otg)
 {
        u32 events = 0, user_events = 0;
-       u32 otg_mask = 0, user_mask = 0;
+       u32 otg_mask = 0, user_mask = 0, phyval;
        enum dwc_otg_state state = DWC_STATE_INVALID;
 
        otg_dbg(otg, "\n");
@@ -444,6 +444,15 @@ static enum dwc_otg_state do_connector_id_status(struct dwc_otg2 *otg)
        otg_write(otg, OEVTEN, OEVT_CONN_ID_STS_CHNG_EVNT);
        otg_write(otg, OCTL, OCTL_PERI_MODE);
 
+       /* This is a hardware workaround.
+        * xHCI RxDetect state is not work well when USB3
+        * PHY under P3 state. So force PHY change to P2 when
+        * xHCI want to perform receiver detection.
+        */
+       phyval = otg_read(otg, GUSB3PIPECTL0);
+       phyval |= GUSB3PIPE_DISRXDETP3;
+       otg_write(otg, GUSB3PIPECTL0, phyval);
+
        msleep(60);
 
 #ifndef SUPPORT_USER_ID_CHANGE_EVENTS

diff --git a/include/linux/usb/dwc_otg3.h b/include/linux/usb/dwc_otg3.h
index 9797d6b..a9e0bef 100644 (file)
--- a/include/linux/usb/dwc_otg3.h
+++ b/include/linux/usb/dwc_otg3.h
@@ -91,6 +91,7 @@ struct dwc_device_par {
 
 #define GUSB3PIPECTL0                           0xc2c0
 #define GUSB3PIPECTL_SUS_EN                     0x20000
+#define GUSB3PIPE_DISRXDETP3                    (1 << 28)
 
 #define GHWPARAMS6                             0xc158
 #define GHWPARAMS6_SRP_SUPPORT_ENABLED         0x0400