[PhaseOrdering] Add test case for PR36760

Ensures that the correct sequence of simplifycfg/instcombine/sroa reduce the IR to just a icmp+select

diff --git a/llvm/test/Transforms/PhaseOrdering/pr36760.ll b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
new file mode 100644 (file)
index 0000000..5f8fb9f
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O2 -S < %s -enable-new-pm=0 | FileCheck %s
+; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
+
+define i64 @PR36760(i64 %a) {
+; CHECK-LABEL: @PR36760(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i64 [[A:%.*]], 0
+; CHECK-NEXT:    [[DOTA:%.*]] = select i1 [[TMP0]], i64 [[A]], i64 0
+; CHECK-NEXT:    ret i64 [[DOTA]]
+;
+entry:
+  %retval = alloca i64, align 8
+  %a.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  %0 = load i64, i64* %a.addr, align 8
+  %cmp = icmp slt i64 %0, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  store i64 0, i64* %retval, align 8
+  br label %return
+
+if.end:
+  %1 = load i64, i64* %a.addr, align 8
+  %shr = ashr i64 %1, 63
+  %2 = load i64, i64* %a.addr, align 8
+  %xor = xor i64 %shr, %2
+  store i64 %xor, i64* %retval, align 8
+  br label %return
+
+return:
+  %3 = load i64, i64* %retval, align 8
+  ret i64 %3
+}