projects
/
platform
/
upstream
/
llvm.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
a1f1a3b
)
[MIPS] Fix DIV/DIVU scheduling classes.
author
Clement Courbet
<courbet@google.com>
Wed, 2 May 2018 13:37:28 +0000
(13:37 +0000)
committer
Clement Courbet
<courbet@google.com>
Wed, 2 May 2018 13:37:28 +0000
(13:37 +0000)
https://reviews.llvm.org/D46356.
llvm-svn: 331354
llvm/lib/Target/Mips/MipsScheduleGeneric.td
patch
|
blob
|
history
diff --git
a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index
4087f1c
..
79c55db
100644
(file)
--- a/
llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/
llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@
-74,12
+74,12
@@
def : ItinRW<[GenericWriteMDUtoGPR], [II_MUL]>;
def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 33;
- let ResourceCycles = [
1,
33];
+ let ResourceCycles = [33];
}
def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 31;
- let ResourceCycles = [
1,
31];
+ let ResourceCycles = [31];
}
def : ItinRW<[GenericWriteDIV], [II_DIV]>;