MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)

The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.

Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 63002a2..089125a 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -252,4 +252,8 @@
 #define cpu_hwrena_impl_bits           0
 #endif
 
+#ifndef cpu_has_perf_cntr_intr_bit
+#define cpu_has_perf_cntr_intr_bit     (cpu_data[0].options & MIPS_CPU_PCI)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 554e2d2..7dc0db8 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -320,7 +320,8 @@ enum cpu_type_enum {
 #define MIPS_CPU_VINT          0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC          0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 #define MIPS_CPU_ULRI          0x00200000 /* CPU has ULRI feature */
-#define MIPS_CPU_RIXI          0x00400000 /* CPU has TLB Read/eXec Inhibit */
+#define MIPS_CPU_PCI           0x00400000 /* CPU has Perf Ctr Int indicator */
+#define MIPS_CPU_RIXI          0x00800000 /* CPU has TLB Read/eXec Inhibit */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 528fda1..04d7560 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -458,6 +458,8 @@
 #define  CAUSEF_IP7            (_ULCAST_(1)   << 15)
 #define  CAUSEB_IV             23
 #define  CAUSEF_IV             (_ULCAST_(1)   << 23)
+#define  CAUSEB_PCI            26
+#define  CAUSEF_PCI            (_ULCAST_(1)   << 26)
 #define  CAUSEB_CE             28
 #define  CAUSEF_CE             (_ULCAST_(3)   << 28)
 #define  CAUSEB_TI             30

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bc58bd1..bd28096 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1194,8 +1194,11 @@ __cpuinit void cpu_probe(void)
                }
        }
 
-       if (cpu_has_mips_r2)
+       if (cpu_has_mips_r2) {
                c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
+               /* R2 has Performance Counter Interrupt indicator */
+               c->options |= MIPS_CPU_PCI;
+       }
        else
                c->srsets = 1;
 

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 8451f04..4ee1111 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1158,7 +1158,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
        int handled = IRQ_NONE;
        struct pt_regs *regs;
 
-       if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+       if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
                return handled;
        /*
         * First we pause the local counters, so that when we are locked