ARM: mvebu: Align the internal registers virtual base to support LPAE

In order to be able to support the LPAE, the internal registers
virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
earlyprintk we map the internal registers and it must be section
aligned.

Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index 865c6d0..df191af 100644 (file)
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -12,7 +12,7 @@
 */
 
 #define ARMADA_370_XP_REGS_PHYS_BASE   0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE   0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE   0xfec00000
 
        .macro  addruart, rp, rv, tmp
        ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE

diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 9783087..2070e1b 100644 (file)
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE   0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE   IOMEM(0xfeb00000)
+#define ARMADA_370_XP_REGS_VIRT_BASE   IOMEM(0xfec00000)
 #define ARMADA_370_XP_REGS_SIZE                SZ_1M
 
 /* These defines can go away once mvebu-mbus has a DT binding */