val rA = RegNext(io.a)
val rB = RegNext(io.b)
val rC = RegNext(io.c)
-
+
mult := rA * rB
add := rC +& mult
-
+
io.y := add
}
when (state === sIdle) {
inflight := 0.U
} .elsewhen (!dec.reset) {
- when (state === sExe && inflight =/= ((1 << pBits) - 1).asUInt) { // overflow check
+ when (state === sReadTensor) { // issue a tensor
inflight := inflight + 1.U
- } .elsewhen (mvc.io.acc_o.data.valid && inflight =/= 0.U) { // underflow check
+ } .elsewhen (mvc.io.acc_o.data.valid) { // commit a tensor
inflight := inflight - 1.U
}
}
*
* Store 1D and 2D tensors from out-scratchpad (SRAM) to main memory (DRAM).
*/
-class TensorStore(tensorType: String = "true", debug: Boolean = false)
+class TensorStore(tensorType: String = "none", debug: Boolean = false)
(implicit p: Parameters) extends Module {
val tp = new TensorParams(tensorType)
val mp = p(ShellKey).memParams
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY