[PowerPC] Pre-commit more tests for `select` codegen. NFC.

diff --git a/llvm/test/CodeGen/PowerPC/select.ll b/llvm/test/CodeGen/PowerPC/select.ll
index 7bfa03e..1b53724 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/select.ll
+++ b/llvm/test/CodeGen/PowerPC/select.ll
@@ -240,3 +240,89 @@ define i64 @f4_sgt_m1(i64 %x) {
   %r = select i1 %c, i64 %x.neg, i64 %x
   ret i64 %r
 }
+
+define i64 @f5(i64 %x, i64 %y) {
+; CHECK-LE-LABEL: f5:
+; CHECK-LE:       # %bb.0:
+; CHECK-LE-NEXT:    li r5, 0
+; CHECK-LE-NEXT:    cmpldi r3, 0
+; CHECK-LE-NEXT:    iseleq r3, r4, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-32-LABEL: f5:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    li r7, 0
+; CHECK-32-NEXT:    or. r3, r4, r3
+; CHECK-32-NEXT:    bc 12, eq, .LBB9_2
+; CHECK-32-NEXT:  # %bb.1:
+; CHECK-32-NEXT:    ori r3, r7, 0
+; CHECK-32-NEXT:    ori r4, r7, 0
+; CHECK-32-NEXT:    blr
+; CHECK-32-NEXT:  .LBB9_2:
+; CHECK-32-NEXT:    addi r3, r5, 0
+; CHECK-32-NEXT:    addi r4, r6, 0
+; CHECK-32-NEXT:    blr
+  %c = icmp eq i64 %x, 0
+  %r = select i1 %c, i64 %y, i64 0
+  ret i64 %r
+}
+
+define i32 @f5_i32(i32 %x, i32 %y) {
+; CHECK-LE-LABEL: f5_i32:
+; CHECK-LE:       # %bb.0:
+; CHECK-LE-NEXT:    li r5, 0
+; CHECK-LE-NEXT:    cmplwi r3, 0
+; CHECK-LE-NEXT:    iseleq r3, r4, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-32-LABEL: f5_i32:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    li r5, 0
+; CHECK-32-NEXT:    cmplwi r3, 0
+; CHECK-32-NEXT:    bc 12, eq, .LBB10_2
+; CHECK-32-NEXT:  # %bb.1:
+; CHECK-32-NEXT:    ori r3, r5, 0
+; CHECK-32-NEXT:    blr
+; CHECK-32-NEXT:  .LBB10_2:
+; CHECK-32-NEXT:    addi r3, r4, 0
+; CHECK-32-NEXT:    blr
+  %c = icmp eq i32 %x, 0
+  %r = select i1 %c, i32 %y, i32 0
+  ret i32 %r
+}
+
+define i64 @f6(i64 %x) {
+; CHECK-LE-LABEL: f6:
+; CHECK-LE:       # %bb.0:
+; CHECK-LE-NEXT:    cntlzd r3, r3
+; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-32-LABEL: f6:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    or r3, r4, r3
+; CHECK-32-NEXT:    cntlzw r3, r3
+; CHECK-32-NEXT:    rlwinm r4, r3, 27, 31, 31
+; CHECK-32-NEXT:    li r3, 0
+; CHECK-32-NEXT:    blr
+  %c = icmp ne i64 %x, 0
+  %r = select i1 %c, i64 0, i64 1
+  ret i64 %r
+}
+
+define i32 @f6_i32(i32 %x) {
+; CHECK-LE-LABEL: f6_i32:
+; CHECK-LE:       # %bb.0:
+; CHECK-LE-NEXT:    cntlzw r3, r3
+; CHECK-LE-NEXT:    srwi r3, r3, 5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-32-LABEL: f6_i32:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    cntlzw r3, r3
+; CHECK-32-NEXT:    rlwinm r3, r3, 27, 31, 31
+; CHECK-32-NEXT:    blr
+  %c = icmp ne i32 %x, 0
+  %r = select i1 %c, i32 0, i32 1
+  ret i32 %r
+}