#define HW_SCOREBOARD // HW Scoreboard should be enabled for ILK and beyond\r
#undef SW_SCOREBOARD // SW Scoreboard should be disabled for ILK and beyond\r
#endif // DEV_CTG\r
-#include "export.inc"\r
+#ifdef BOOTSTRAP\r
+# ifdef ENABLE_ILDB\r
+# define ALL_SPAWNED_UV_ILDB_FRAME_IP 0\r
+# define SLEEP_ENTRY_UV_ILDB_FRAME_IP 0\r
+# define POST_SLEEP_UV_ILDB_FRAME_IP 0\r
+# define ALL_SPAWNED_Y_ILDB_FRAME_IP 0\r
+# define SLEEP_ENTRY_Y_ILDB_FRAME_IP 0\r
+# define POST_SLEEP_Y_ILDB_FRAME_IP 0\r
+# endif\r
+#elif defined(DEV_ILK)\r
+# include "export.inc.gen5"\r
+#elif defined(DEV_CTG)\r
+# include "export.inc"\r
+#endif\r
#if defined(_EXPORT)\r
#include "AllAVC_Export.inc"\r
#elif defined(_BUILD)\r
rm $*.g4m
$(INTEL_MC_GEN5_ASM): $(INTEL_MC_ASM) $(INTEL_MC_INC) $(INTEL_ILDB_ASM)
- cpp -D DEV_ILK -I ../ildb/ AllAVC.asm > _mc.$@; \
- ../../gpp.py _mc.$@ $@ ; \
- rm _mc.$@
+ cpp -DDEV_ILK -DBOOTSTRAP -I ../ildb/ AllAVC.asm > _mc0.$@ && \
+ ../../gpp.py _mc0.$@ $@ && \
+ intel-gen4asm -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $@ \
+ -o /dev/null && \
+ mv tmp.$(INTEL_MC_EXPORT_GEN5) $(INTEL_MC_EXPORT_GEN5) && \
+ cpp -DDEV_ILK -I ../ildb/ AllAVC.asm > _mc1.$@ && \
+ ../../gpp.py _mc1.$@ $@ && \
+ rm _mc0.$@ _mc1.$@
$(INTEL_MC_G4B_GEN5): $(INTEL_MC_GEN5_ASM)
- intel-gen4asm -l list -a -e _export.inc.gen5 -o $@ -g 5 $<; \
- cat _export.inc.gen5 | sed "s/_IP/_IP_GEN5/g" > $(INTEL_MC_EXPORT_GEN5); \
- rm _export.inc.gen5
+ intel-gen4asm -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $< \
+ -o $@ && \
+ cat tmp.$(INTEL_MC_EXPORT_GEN5) | sed "s/_IP/_IP_GEN5/g" \
+ > $(INTEL_MC_EXPORT_GEN5) && \
+ rm tmp.$(INTEL_MC_EXPORT_GEN5)
$(INTEL_G4B): $(INTEL_G4I)