SHA: Add SHA instructions
authorJin Kyu Song <jin.kyu.song@intel.com>
Wed, 16 Oct 2013 02:44:03 +0000 (19:44 -0700)
committerJin Kyu Song <jin.kyu.song@intel.com>
Wed, 20 Nov 2013 19:29:42 +0000 (11:29 -0800)
New instruction extensions of SHA family are added.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
insns.dat
insns.h

index 8462211..f60ea8e 100644 (file)
--- a/insns.dat
+++ b/insns.dat
@@ -4171,6 +4171,15 @@ BNDSTX      mem128,bndreg          [mr:            0f 1b /r ]  MPX,MIB,SO,FUTURE
 BNDSTX      mem128,reg64,bndreg    [mxr:           0f 1b /r ]  MPX,MIB,FUTURE
 BNDSTX      mem128,bndreg,reg64    [mrx:           0f 1b /r ]  MPX,MIB,FUTURE
 
+; SHA instructions
+SHA1RNDS4   xmmreg,xmmrm128,imm8    [rmi:    0f 3a cc /r ib ]    SHA,FUTURE
+SHA1NEXTE   xmmreg,xmmrm128         [rm:        0f 38 c8 /r ]    SHA,FUTURE
+SHA1MSG1    xmmreg,xmmrm128         [rm:        0f 38 c9 /r ]    SHA,FUTURE
+SHA1MSG2    xmmreg,xmmrm128         [rm:        0f 38 ca /r ]    SHA,FUTURE
+SHA256RNDS2 xmmreg,xmmrm128,xmm0    [rm-:       0f 38 cb /r ]    SHA,FUTURE
+SHA256MSG1  xmmreg,xmmrm128         [rm:        0f 38 cc /r ]    SHA,FUTURE
+SHA256MSG2  xmmreg,xmmrm128         [rm:        0f 38 cd /r ]    SHA,FUTURE
+
 ;# Systematic names for the hinting nop instructions
 ; These should be last in the file
 HINT_NOP0      rm16                            [m:     o16 0f 18 /0]                           P6,UNDOC
diff --git a/insns.h b/insns.h
index 6e94f3d..8b725ae 100644 (file)
--- a/insns.h
+++ b/insns.h
@@ -133,6 +133,7 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_AVX512ER     (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */
 #define IF_AVX512PF     (0x1800000000UL|IF_AVX512) /* AVX-512 Prefetch instructions */
 #define IF_MPX          0x1900000000UL    /* MPX instructions */
+#define IF_SHA          0x1A00000000UL    /* SHA instructions */
 #define IF_INSMASK      0xFF00000000UL    /* the mask for instruction set types */
 #define IF_PMASK        0xFF000000UL    /* the mask for processor types */
 #define IF_PLEVEL       0x0F000000UL    /* the mask for processor instr. level */