phy: cadence: Sierra: Fix to get correct parent for mux clocks

Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.

Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 728abd1..abdbc6e 100644 (file)
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -257,7 +257,10 @@ static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
        [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
 };
 
-static u32 cdns_sierra_pll_mux_table[] = { 0, 1 };
+static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {
+       [CMN_PLLLC] = { 0, 1 },
+       [CMN_PLLLC1] = { 1, 0 },
+};
 
 enum cdns_sierra_phy_type {
        TYPE_NONE,
@@ -567,11 +570,25 @@ static const struct phy_ops ops = {
 static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
 {
        struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
+       struct regmap_field *plllc1en_field = mux->plllc1en_field;
+       struct regmap_field *termen_field = mux->termen_field;
        struct regmap_field *field = mux->pfdclk_sel_preg;
        unsigned int val;
+       int index;
 
        regmap_field_read(field, &val);
-       return clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table, 0, val);
+
+       if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
+               index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
+               if (index == 1) {
+                       regmap_field_write(plllc1en_field, 1);
+                       regmap_field_write(termen_field, 1);
+               }
+       } else {
+               index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
+       }
+
+       return index;
 }
 
 static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
@@ -589,7 +606,11 @@ static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
                ret |= regmap_field_write(termen_field, 1);
        }
 
-       val = cdns_sierra_pll_mux_table[index];
+       if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
+               val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index];
+       else
+               val = cdns_sierra_pll_mux_table[CMN_PLLLC][index];
+
        ret |= regmap_field_write(field, val);
 
        return ret;
@@ -627,8 +648,8 @@ static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
        for (i = 0; i < num_parents; i++) {
                clk = sp->input_clks[pll_mux_parent_index[clk_index][i]];
                if (IS_ERR_OR_NULL(clk)) {
-                       dev_err(dev, "No parent clock for derived_refclk\n");
-                       return PTR_ERR(clk);
+                       dev_err(dev, "No parent clock for PLL mux clocks\n");
+                       return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
                }
                parent_names[i] = __clk_get_name(clk);
        }