+2019-05-17 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
+
+ * config/mips/mips.c (mips_dwarf_frame_reg_mode): Replace
+ TARGET_FLOAT64 with !TARGET_FLOAT32, thus handling both fp64
+ and fpxx modes.
+
2019-05-17 H.J. Lu <hongjiu.lu@intel.com>
PR target/90497
{
machine_mode mode = default_dwarf_frame_reg_mode (regno);
- if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
+ if (FP_REG_P (regno) && mips_abi == ABI_32 && !TARGET_FLOAT32)
mode = SImode;
return mode;
+2019-05-17 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
+
+ * g++.dg/eh/o32-fp.C: New.
+ * gcc.target/mips/dwarfregtable-1.c: New.
+ * gcc.target/mips/dwarfregtable-2.c: New.
+ * gcc.target/mips/dwarfregtable-3.c: New.
+ * gcc.target/mips/dwarfregtable-4.c: New.
+ * gcc.target/mips/dwarfregtable.h: New.
+
2019-05-17 H.J. Lu <hongjiu.lu@intel.com>
* gcc.target/x86_64/abi/test_varargs-m128.c: New file.
--- /dev/null
+// Test whether call saved float are restored properly for O32 ABI
+// { dg-do run { target { { { mips*-*-linux* } && hard_float } && { ! mips64 } } } }
+// { dg-options "-O2" }
+
+void __attribute__((noinline))
+bar (void)
+{
+ throw 1;
+}
+
+void __attribute__((noinline))
+foo (void)
+{
+ register double f20 __asm__ ("f20") = 0.0;
+ register double f22 __asm__ ("f22") = 0.0;
+ register double f24 __asm__ ("f24") = 0.0;
+ register double f26 __asm__ ("f26") = 0.0;
+ register double f28 __asm__ ("f28") = 0.0;
+ register double f30 __asm__ ("f30") = 0.0;
+ __asm__ __volatile__("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+ bar ();
+}
+
+int
+main (void)
+{
+ register double f20 __asm__ ("f20") = 12.0;
+ register double f22 __asm__ ("f22") = 13.0;
+ register double f24 __asm__ ("f24") = 14.0;
+ register double f26 __asm__ ("f26") = 15.0;
+ register double f28 __asm__ ("f28") = 16.0;
+ register double f30 __asm__ ("f30") = 17.0;
+
+ try
+ {
+ foo ();
+ }
+ catch (...)
+ {
+ __asm__ ("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+ }
+
+ if (f20 != 12.0 || f22 != 13.0 || f24 != 14.0
+ || f26 != 15.0 || f28 != 16.0 || f30 != 17.0)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* Check if content of dwarf reg size table matches the expected. */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfp32" } */
+
+#include "dwarfregtable.h"
--- /dev/null
+/* Check if content of dwarf reg size table matches the expected. */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfpxx" } */
+
+#include "dwarfregtable.h"
--- /dev/null
+/* Check if content of dwarf reg size table matches the expected. */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfp64" } */
+
+#include "dwarfregtable.h"
--- /dev/null
+/* Check if content of dwarf reg size table matches the expected. */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfp64 -modd-spreg" } */
+
+#include "dwarfregtable.h"
--- /dev/null
+
+typedef unsigned Unwind_Word __attribute__((__mode__(__unwind_word__)));
+
+#define DWARF_FRAME_REGISTERS 188
+
+static unsigned char ref_dwarf_reg_size_table[DWARF_FRAME_REGISTERS + 1] =
+ {
+ [0 ... 66] = sizeof (Unwind_Word),
+ [80 ... 181] = sizeof (Unwind_Word)
+ };
+
+static unsigned char dwarf_reg_size_table[DWARF_FRAME_REGISTERS + 1] = {};
+
+int
+main (void)
+{
+ __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
+ if (__builtin_memcmp (ref_dwarf_reg_size_table,
+ dwarf_reg_size_table, DWARF_FRAME_REGISTERS + 1) != 0)
+ __builtin_abort ();
+ return 0;
+}