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travis: Wire Xilinx Versal Virt platform
author
Michal Simek
<michal.simek@xilinx.com>
Thu, 20 Dec 2018 07:40:25 +0000
(08:40 +0100)
committer
Michal Simek
<michal.simek@xilinx.com>
Thu, 24 Jan 2019 09:03:44 +0000
(10:03 +0100)
Test Xilinx Versal Virt platform running on the v3.1.0 Qemu.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
.travis.yml
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diff --git
a/.travis.yml
b/.travis.yml
index
59e615a
..
49a7fa9
100644
(file)
--- a/
.travis.yml
+++ b/
.travis.yml
@@
-463,6
+463,13
@@
matrix:
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
+ - name: "test/py xilinx_versal_virt"
+ env:
+ - TEST_PY_BD="xilinx_versal_virt"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^xilinx_versal_virt$"
- name: "test/py xtfpga"
env:
- TEST_PY_BD="xtfpga"