Revert "drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)"

This reverts commit 9ed2c993d723129f85101e51b2ccc36ef5400a67.

SET_CONFIG_REG writes to memory if register shadowing is enabled,
causing a VM fault.

NGG streamout is unstable anyway, so all UMDs should use legacy
streamout. I think Mesa is the only driver using NGG streamout.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
index df8a235..f6ac1e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
@@ -32,7 +32,6 @@ struct amdgpu_gds {
        uint32_t gws_size;
        uint32_t oa_size;
        uint32_t gds_compute_max_wave_id;
-       uint32_t vgt_gs_max_wave_id;
 };
 
 struct amdgpu_gds_reg_offset {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 32773b7..f41287f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4206,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
        u32 header, control = 0;
 
-       /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
-        * This resets the wave ID counters. (needed by transform feedback)
-        * TODO: This might only be needed on a VMID switch when we change
-        *       the GDS OA mapping, not sure.
-        */
-       amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
-       amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
-
        if (ib->flags & AMDGPU_IB_FLAG_CE)
                header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
        else
@@ -4961,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
                5 + /* HDP_INVL */
                8 + 8 + /* FENCE x2 */
                2, /* SWITCH_BUFFER */
-       .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */
+       .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
        .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
        .emit_fence = gfx_v10_0_ring_emit_fence,
        .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
@@ -5112,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
        default:
                adev->gds.gds_size = 0x10000;
                adev->gds.gds_compute_max_wave_id = 0x4ff;
-               adev->gds.vgt_gs_max_wave_id = 0x3ff;
                break;
        }