drm/amdkfd: Record vmid pasid mapping in the driver for non HWS mode

This makes possible the vmid pasid mapping query through software.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 2ad3b9e..553c45e 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -195,20 +195,30 @@ static int allocate_vmid(struct device_queue_manager *dqm,
                        struct qcm_process_device *qpd,
                        struct queue *q)
 {
-       int bit, allocated_vmid;
+       int allocated_vmid = -1, i;
 
-       if (dqm->vmid_bitmap == 0)
-               return -ENOMEM;
+       for (i = dqm->dev->vm_info.first_vmid_kfd;
+                       i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
+               if (!dqm->vmid_pasid[i]) {
+                       allocated_vmid = i;
+                       break;
+               }
+       }
+
+       if (allocated_vmid < 0) {
+               pr_err("no more vmid to allocate\n");
+               return -ENOSPC;
+       }
+
+       pr_debug("vmid allocated: %d\n", allocated_vmid);
+
+       dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
 
-       bit = ffs(dqm->vmid_bitmap) - 1;
-       dqm->vmid_bitmap &= ~(1 << bit);
+       set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
 
-       allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
-       pr_debug("vmid allocation %d\n", allocated_vmid);
        qpd->vmid = allocated_vmid;
        q->properties.vmid = allocated_vmid;
 
-       set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
        program_sh_mem_settings(dqm, qpd);
 
        /* qpd->page_table_base is set earlier when register_process()
@@ -249,8 +259,6 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
                                struct qcm_process_device *qpd,
                                struct queue *q)
 {
-       int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
-
        /* On GFX v7, CP doesn't flush TC at dequeue */
        if (q->device->device_info->asic_family == CHIP_HAWAII)
                if (flush_texture_cache_nocpsch(q->device, qpd))
@@ -260,8 +268,8 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
 
        /* Release the vmid mapping */
        set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
+       dqm->vmid_pasid[qpd->vmid] = 0;
 
-       dqm->vmid_bitmap |= (1 << bit);
        qpd->vmid = 0;
        q->properties.vmid = 0;
 }
@@ -880,7 +888,8 @@ static int initialize_nocpsch(struct device_queue_manager *dqm)
                                dqm->allocated_queues[pipe] |= 1 << queue;
        }
 
-       dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
+       memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
+
        dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
        dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
 

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index 90db2c9..2eaea6b 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -32,6 +32,8 @@
 #include "kfd_mqd_manager.h"
 
 
+#define VMID_NUM 16
+
 struct device_process_node {
        struct qcm_process_device *qpd;
        struct list_head list;
@@ -185,7 +187,8 @@ struct device_queue_manager {
        unsigned int            *allocated_queues;
        uint64_t                sdma_bitmap;
        uint64_t                xgmi_sdma_bitmap;
-       unsigned int            vmid_bitmap;
+       /* the pasid mapping for each kfd vmid */
+       uint16_t                vmid_pasid[VMID_NUM];
        uint64_t                pipelines_addr;
        struct kfd_mem_obj      *pipeline_mem;
        uint64_t                fence_gpu_addr;