ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
ae_dev->dev_specs.rss_key_size = HCLGE_RSS_KEY_SIZE;
+ ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
}
static void hclge_parse_dev_specs(struct hclge_dev *hdev,
ae_dev->dev_specs.rss_ind_tbl_size =
le16_to_cpu(req0->rss_ind_tbl_size);
ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
+ ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
}
static int hclge_query_dev_specs(struct hclge_dev *hdev)
#define HCLGE_SHAPER_BS_U_DEF 5
#define HCLGE_SHAPER_BS_S_DEF 20
-#define HCLGE_ETHER_MAX_RATE 100000
-
/* hclge_shaper_para_calc: calculate ir parameter for the shaper
* @ir: Rate to be config, its unit is Mbps
* @shaper_level: the shaper level. eg: port, pg, priority, queueset
* @ir_b: IR_B parameter of IR shaper
* @ir_u: IR_U parameter of IR shaper
* @ir_s: IR_S parameter of IR shaper
+ * @max_tm_rate: max tm rate is available to config
*
* the formula:
*
* @return: 0: calculate sucessful, negative: fail
*/
static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
- u8 *ir_b, u8 *ir_u, u8 *ir_s)
+ u8 *ir_b, u8 *ir_u, u8 *ir_s,
+ u32 max_tm_rate)
{
#define DIVISOR_CLK (1000 * 8)
#define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
/* Calc tick */
if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
- ir > HCLGE_ETHER_MAX_RATE)
+ ir > max_tm_rate)
return -EINVAL;
tick = tick_array[shaper_level];
ret = hclge_shaper_para_calc(hdev->hw.mac.speed,
HCLGE_SHAPER_LVL_PORT,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ hdev->ae_dev->dev_specs.max_tm_rate);
if (ret)
return ret;
int ret, i;
if (!max_tx_rate)
- max_tx_rate = HCLGE_ETHER_MAX_RATE;
+ max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ hdev->ae_dev->dev_specs.max_tm_rate);
if (ret)
return ret;
hdev->tm_info.pg_info[i].pg_id = i;
hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
- hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
+ hdev->tm_info.pg_info[i].bw_limit =
+ hdev->ae_dev->dev_specs.max_tm_rate;
if (i != 0)
continue;
static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
{
+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
u8 ir_u, ir_b, ir_s;
u32 shaper_para;
int ret;
ret = hclge_shaper_para_calc(
hdev->tm_info.pg_info[i].bw_limit,
HCLGE_SHAPER_LVL_PG,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ max_tm_rate);
if (ret)
return ret;
static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
{
+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
u8 ir_u, ir_b, ir_s;
u32 shaper_para;
int ret;
ret = hclge_shaper_para_calc(
hdev->tm_info.tc_info[i].bw_limit,
HCLGE_SHAPER_LVL_PRI,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ max_tm_rate);
if (ret)
return ret;
int ret;
ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ hdev->ae_dev->dev_specs.max_tm_rate);
if (ret)
return ret;
{
struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
struct hclge_dev *hdev = vport->back;
+ u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
u8 ir_u, ir_b, ir_s;
u32 i;
int ret;
ret = hclge_shaper_para_calc(
hdev->tm_info.tc_info[i].bw_limit,
HCLGE_SHAPER_LVL_QSET,
- &ir_b, &ir_u, &ir_s);
+ &ir_b, &ir_u, &ir_s,
+ max_tm_rate);
if (ret)
return ret;
}