Remove the sysclk and sysclk_src checking in the function set_sysclk() to
prevent the PLL power off. It is not getting re-programmed during
subsequent runs after the first run (in BIAS_OFF stage).
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Link: https://lore.kernel.org/r/20220210071900.17287-1-oder_chiou@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
unsigned int reg_val = 0;
unsigned int pll_bit = 0;
- if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
- return 0;
-
switch (clk_id) {
case RT5640_SCLK_S_MCLK:
reg_val |= RT5640_SCLK_SRC_MCLK;