return false;
}
+// Return true if all users of this SDNode* only consume the lower \p Bits.
+// This can be used to form W instructions for add/sub/mul/shl even when the
+// root isn't a sext_inreg. This can allow the ADDW/SUBW/MULW/SLLIW to CSE if
+// SimplifyDemandedBits has made it so some users see a sext_inreg and some
+// don't. The sext_inreg+add/sub/mul/shl will get selected, but still leave
+// the add/sub/mul/shl to become non-W instructions. By checking the users we
+// may be able to use a W instruction and CSE with the other instruction if
+// this has happened. We could try to detect that the CSE opportunity exists
+// before doing this, but that would be more complicated.
+// TODO: Does this need to look through AND/OR/XOR to their users to find more
+// opportunities.
+bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
+ assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB ||
+ Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL) &&
+ "Unexpected opcode");
+
+ for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {
+ SDNode *User = *UI;
+ // Users of this node should have already been instruction selected
+ if (!User->isMachineOpcode())
+ return false;
+
+ // TODO: Add more opcodes?
+ switch (User->getMachineOpcode()) {
+ default:
+ return false;
+ case RISCV::ADDW:
+ case RISCV::ADDIW:
+ case RISCV::SUBW:
+ case RISCV::MULW:
+ case RISCV::SLLW:
+ case RISCV::SLLIW:
+ case RISCV::SRAW:
+ case RISCV::SRAIW:
+ case RISCV::SRLW:
+ case RISCV::SRLIW:
+ case RISCV::DIVW:
+ case RISCV::DIVUW:
+ case RISCV::REMW:
+ case RISCV::REMUW:
+ case RISCV::ROLW:
+ case RISCV::RORW:
+ case RISCV::RORIW:
+ case RISCV::CLZW:
+ case RISCV::CTZW:
+ case RISCV::CPOPW:
+ case RISCV::SLLIUW:
+ if (Bits < 32)
+ return false;
+ break;
+ case RISCV::SLLI:
+ // SLLI only uses the lower (XLen - ShAmt) bits.
+ if (Bits < Subtarget->getXLen() - User->getConstantOperandVal(1))
+ return false;
+ break;
+ case RISCV::ADDUW:
+ case RISCV::SH1ADDUW:
+ case RISCV::SH2ADDUW:
+ case RISCV::SH3ADDUW:
+ // The first operand to add.uw/shXadd.uw is implicitly zero extended from
+ // 32 bits.
+ if (UI.getOperandNo() != 0 || Bits < 32)
+ return false;
+ break;
+ case RISCV::SB:
+ if (UI.getOperandNo() != 0 || Bits < 8)
+ return false;
+ break;
+ case RISCV::SH:
+ if (UI.getOperandNo() != 0 || Bits < 16)
+ return false;
+ break;
+ case RISCV::SW:
+ if (UI.getOperandNo() != 0 || Bits < 32)
+ return false;
+ break;
+ }
+ }
+
+ return true;
+}
+
// Select VL as a 5 bit immediate or a value that will become a register. This
// allows us to choose betwen VSETIVLI or VSETVLI later.
bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
bool selectSExti32(SDValue N, SDValue &Val);
bool selectZExti32(SDValue N, SDValue &Val);
+ bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const;
+ bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
+
bool selectVLOp(SDValue N, SDValue &VL);
bool selectVSplat(SDValue N, SDValue &SplatVal);
(SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
}
+// PatFrag to allow ADDW/SUBW/MULW/SLLW to be selected from i64 add/sub/mul/shl
+// if only the lower 32 bits of their result is used.
+class overflowingbinopw<SDPatternOperator operator>
+ : PatFrag<(ops node:$lhs, node:$rhs),
+ (operator node:$lhs, node:$rhs), [{
+ return hasAllWUsers(Node);
+}]>;
+
let Predicates = [IsRV64] in {
/// sext and zext
def : PatGprGpr<shiftopw<riscv_srlw>, SRLW>;
def : PatGprGpr<shiftopw<riscv_sraw>, SRAW>;
+// Select W instructions without sext_inreg if only the lower 32 bits of the
+// result are used.
+def : PatGprGpr<overflowingbinopw<add>, ADDW>;
+def : PatGprSimm12<overflowingbinopw<add>, ADDIW>;
+def : PatGprGpr<overflowingbinopw<sub>, SUBW>;
+def : PatGprImm<overflowingbinopw<shl>, SLLIW, uimm5>;
+
/// Loads
defm : LdPat<sextloadi32, LW, i64>;
def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
(MULW GPR:$rs1, GPR:$rs2)>;
+// Select W instructions without sext_inreg if only the lower 32-bits of the
+// result are used.
+def : PatGprGpr<overflowingbinopw<mul>, MULW>;
+
def : PatGprGpr<riscv_divw, DIVW>;
def : PatGprGpr<riscv_divuw, DIVUW>;
def : PatGprGpr<riscv_remuw, REMUW>;
;
; RV64I-LABEL: add_small_const:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: jalr zero, 0(ra)
;
; RV64C-LABEL: add_small_const:
; RV64C: # %bb.0:
-; RV64C-NEXT: c.addi a0, 1
+; RV64C-NEXT: c.addiw a0, 1
; RV64C-NEXT: c.slli a0, 56
; RV64C-NEXT: c.srai a0, 56
; RV64C-NEXT: c.jr ra
; RV64C: # %bb.0:
; RV64C-NEXT: c.lui a1, 1
; RV64C-NEXT: c.addiw a1, -1
-; RV64C-NEXT: c.add a0, a1
+; RV64C-NEXT: c.addw a0, a1
; RV64C-NEXT: c.slli a0, 48
; RV64C-NEXT: c.srai a0, 48
; RV64C-NEXT: c.jr ra
; RV64C: # %bb.0:
; RV64C-NEXT: c.lui a1, 8
; RV64C-NEXT: c.addiw a1, -1
-; RV64C-NEXT: c.add a0, a1
+; RV64C-NEXT: c.addw a0, a1
; RV64C-NEXT: c.slli a0, 48
; RV64C-NEXT: c.srai a0, 48
; RV64C-NEXT: c.jr ra
;
; RV64I-LABEL: add_non_machine_type:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 256
+; RV64I-NEXT: addiw a0, a0, 256
; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: srai a0, a0, 40
; RV64I-NEXT: jalr zero, 0(ra)
;
; RV64C-LABEL: add_non_machine_type:
; RV64C: # %bb.0:
-; RV64C-NEXT: addi a0, a0, 256
+; RV64C-NEXT: addiw a0, a0, 256
; RV64C-NEXT: c.slli a0, 52
; RV64C-NEXT: c.srai a0, 40
; RV64C-NEXT: c.jr ra
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1096
-; RV64I-NEXT: add a2, a0, a1
-; RV64I-NEXT: lui a3, %hi(gv0)
; RV64I-NEXT: addw a0, a0, a1
-; RV64I-NEXT: sw a2, %lo(gv0)(a3)
+; RV64I-NEXT: lui a1, %hi(gv0)
+; RV64I-NEXT: sw a0, %lo(gv0)(a1)
; RV64I-NEXT: ret
%b = add nsw i32 %a, 3000
store i32 %b, i32* @gv0, align 4
; RV64I-NEXT: lw a3, %lo(gb)(a2)
; RV64I-NEXT: lui a4, 1
; RV64I-NEXT: addiw a4, a4, -1096
-; RV64I-NEXT: add a1, a1, a4
-; RV64I-NEXT: add a3, a3, a4
+; RV64I-NEXT: addw a1, a1, a4
+; RV64I-NEXT: addw a3, a3, a4
; RV64I-NEXT: sw a1, %lo(ga)(a0)
; RV64I-NEXT: sw a3, %lo(gb)(a2)
; RV64I-NEXT: ret
; RV64IM-LABEL: add_mul_trans_accept_1:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 11
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: addiw a0, a0, 407
; RV64IM-NEXT: ret
%tmp0 = add i32 %x, 37
; RV64IM-LABEL: add_mul_trans_accept_2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 13
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: lui a1, 28
; RV64IM-NEXT: addiw a1, a1, 1701
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-LABEL: add_mul_trans_reject_1:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 19
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: lui a1, 9
; RV64IM-NEXT: addiw a1, a1, 585
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 792
; RV64IM-NEXT: addiw a1, a1, -1709
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: lui a1, 1014660
; RV64IM-NEXT: addiw a1, a1, -1891
; RV64IM-NEXT: addw a0, a0, a1
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_release_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_release_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_and_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_and_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_nand_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_or_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_or_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umax_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_xchg_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_or_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_or_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umax_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
-; RV64I-NEXT: add a0, t2, a0
-; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: addw a0, t2, a0
+; RV64I-NEXT: addw a0, a0, a2
; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: xor a2, a3, a7
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: seqz a1, a1
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: add a0, a0, a5
-; RV64I-NEXT: add a0, a0, a6
+; RV64I-NEXT: addw a0, a1, a0
+; RV64I-NEXT: addw a0, a0, a5
+; RV64I-NEXT: addw a0, a0, a6
; RV64I-NEXT: addw a0, a0, t0
; RV64I-NEXT: ret
%a_ext = zext i8 %a to i32
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 29
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 3
; RV64I-NEXT: ret
;
; RV64IM: # %bb.0:
; RV64IM-NEXT: sraiw a1, a0, 31
; RV64IM-NEXT: srliw a1, a1, 29
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: sraiw a0, a0, 3
; RV64IM-NEXT: ret
%1 = sdiv i32 %a, 8
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 16
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: ret
;
; RV64IM: # %bb.0:
; RV64IM-NEXT: sraiw a1, a0, 31
; RV64IM-NEXT: srliw a1, a1, 16
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: sraiw a0, a0, 16
; RV64IM-NEXT: ret
%1 = sdiv i32 %a, 65536
; RV64I-NEXT: srai a1, a1, 56
; RV64I-NEXT: srli a1, a1, 12
; RV64I-NEXT: andi a1, a1, 7
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 59
; RV64I-NEXT: ret
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: srli a1, a1, 12
; RV64IM-NEXT: andi a1, a1, 7
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 59
; RV64IM-NEXT: ret
; RV64I-NEXT: srai a1, a1, 48
; RV64I-NEXT: srli a1, a1, 28
; RV64I-NEXT: andi a1, a1, 7
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 51
; RV64I-NEXT: ret
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: srli a1, a1, 28
; RV64IM-NEXT: andi a1, a1, 7
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 51
; RV64IM-NEXT: ret
;
; RV64I-LABEL: mul_constant:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 2
+; RV64I-NEXT: slliw a1, a0, 2
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IM-LABEL: mul_constant:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 2
+; RV64IM-NEXT: slliw a1, a0, 2
; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: ret
%1 = mul i32 %a, 5
;
; RV64I-LABEL: muli32_p65:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 6
+; RV64I-NEXT: slliw a1, a0, 6
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p65:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 6
+; RV64IM-NEXT: slliw a1, a0, 6
; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: ret
%1 = mul i32 %a, 65
;
; RV64I-LABEL: muli32_p63:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 6
+; RV64I-NEXT: slliw a1, a0, 6
; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p63:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 6
+; RV64IM-NEXT: slliw a1, a0, 6
; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: ret
%1 = mul i32 %a, 63
;
; RV64I-LABEL: muli32_m63:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 6
+; RV64I-NEXT: slliw a1, a0, 6
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_m63:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 6
+; RV64IM-NEXT: slliw a1, a0, 6
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, -63
;
; RV64I-LABEL: muli32_m65:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 6
-; RV64I-NEXT: add a0, a1, a0
+; RV64I-NEXT: slliw a1, a0, 6
+; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_m65:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 6
-; RV64IM-NEXT: add a0, a1, a0
+; RV64IM-NEXT: slliw a1, a0, 6
+; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: negw a0, a0
; RV64IM-NEXT: ret
%1 = mul i32 %a, -65
;
; RV64I-LABEL: muli32_p4352:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: slli a0, a0, 12
+; RV64I-NEXT: slliw a1, a0, 8
+; RV64I-NEXT: slliw a0, a0, 12
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p4352:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 8
-; RV64IM-NEXT: slli a0, a0, 12
+; RV64IM-NEXT: slliw a1, a0, 8
+; RV64IM-NEXT: slliw a0, a0, 12
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 4352
;
; RV64I-LABEL: muli32_p3840:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: slli a0, a0, 12
+; RV64I-NEXT: slliw a1, a0, 8
+; RV64I-NEXT: slliw a0, a0, 12
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p3840:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 8
-; RV64IM-NEXT: slli a0, a0, 12
+; RV64IM-NEXT: slliw a1, a0, 8
+; RV64IM-NEXT: slliw a0, a0, 12
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 3840
;
; RV64I-LABEL: muli32_m3840:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 12
-; RV64I-NEXT: slli a0, a0, 8
+; RV64I-NEXT: slliw a1, a0, 12
+; RV64I-NEXT: slliw a0, a0, 8
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_m3840:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a1, a0, 12
-; RV64IM-NEXT: slli a0, a0, 8
+; RV64IM-NEXT: slliw a1, a0, 12
+; RV64IM-NEXT: slliw a0, a0, 8
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, -3840
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: mulw a0, a0, a0
-; CHECK-NEXT: addi a0, a0, 1
-; CHECK-NEXT: mul a0, a0, a0
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: addiw a0, a0, 1
+; CHECK-NEXT: mulw a0, a0, a0
+; CHECK-NEXT: addw a0, a0, a2
+; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: sllw a0, a0, a1
; CHECK-NEXT: ret
%b = mul i32 %x, %x
define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: zext_addw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_addw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_addw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_addw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_addw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_addw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_addw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_addw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_addw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: zext_subw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_subw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_subw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_subw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_subw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_subw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_subw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_subw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_subw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
; RV64I-LABEL: zext_addiw_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 7
+; RV64I-NEXT: addiw a0, a0, 7
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: zext_addiw_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 8
+; RV64I-NEXT: addiw a0, a0, 8
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: zext_addiw_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 9
+; RV64I-NEXT: addiw a0, a0, 9
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
; CHECK-NEXT: bge a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: addi a3, a0, 1
-; CHECK-NEXT: mul a3, a2, a3
-; CHECK-NEXT: sub a1, a1, a0
-; CHECK-NEXT: addi a1, a1, -2
+; CHECK-NEXT: addw a2, a2, a1
+; CHECK-NEXT: addiw a3, a0, 1
+; CHECK-NEXT: mulw a3, a2, a3
+; CHECK-NEXT: subw a1, a1, a0
+; CHECK-NEXT: addiw a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: mulhu a1, a2, a1
; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: add a0, a3, a0
+; CHECK-NEXT: addw a0, a3, a0
; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: bge a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: mul a2, a3, a2
-; CHECK-NEXT: sub a1, a1, a0
-; CHECK-NEXT: addi a1, a1, -2
+; CHECK-NEXT: addw a3, a2, a1
+; CHECK-NEXT: mulw a2, a3, a2
+; CHECK-NEXT: subw a1, a1, a0
+; CHECK-NEXT: addiw a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: mulhu a1, a3, a1
; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: sub a0, a2, a0
+; CHECK-NEXT: subw a0, a2, a0
; CHECK-NEXT: subw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2:
define zeroext i32 @zext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: zext_mulw_aext_aext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64IM-LABEL: zext_mulw_aext_sext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64IM-LABEL: zext_mulw_aext_zext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64IM-LABEL: zext_mulw_sext_aext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64IM-LABEL: zext_mulw_sext_sext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64IM-LABEL: zext_mulw_sext_zext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64IM-LABEL: zext_mulw_zext_aext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64IM-LABEL: zext_mulw_zext_sext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
define zeroext i32 @zext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64IM-LABEL: zext_mulw_zext_zext:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
; RV64I-LABEL: rol_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a2, a0, a1
-; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
; RV64I-LABEL: rol_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a3, a0, a1
-; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: sllw a2, a1, a0
-; RV64I-NEXT: neg a0, a0
+; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
; RV64I-LABEL: ror_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a2, a0, a1
-; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
; RV64I-LABEL: ror_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a3, a0, a1
-; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: srlw a2, a1, a0
-; RV64I-NEXT: neg a0, a0
+; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64B-LABEL: log2_ceil_i32:
; RV64B: # %bb.0:
-; RV64B-NEXT: addi a0, a0, -1
+; RV64B-NEXT: addiw a0, a0, -1
; RV64B-NEXT: clzw a0, a0
; RV64B-NEXT: addi a1, zero, 32
; RV64B-NEXT: sub a0, a1, a0
;
; RV64ZBB-LABEL: log2_ceil_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: addi a0, a0, -1
+; RV64ZBB-NEXT: addiw a0, a0, -1
; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: addi a1, zero, 32
; RV64ZBB-NEXT: sub a0, a1, a0
; LMULMAX2-RV64-NEXT: addi a4, a4, 257
; LMULMAX2-RV64-NEXT: mul a5, a5, a4
; LMULMAX2-RV64-NEXT: srli a5, a5, 56
-; LMULMAX2-RV64-NEXT: addi a5, a5, -56
+; LMULMAX2-RV64-NEXT: addiw a5, a5, -56
; LMULMAX2-RV64-NEXT: sb a5, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 15
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 31(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 14
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 30(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 13
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 29(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 12
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 28(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 11
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 27(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 10
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 26(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 9
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 25(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 8
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 24(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 23(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 22(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 21(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 20(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 19(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 18(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 17(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
; LMULMAX1-RV64-NEXT: addi a4, a4, 257
; LMULMAX1-RV64-NEXT: mul a5, a5, a4
; LMULMAX1-RV64-NEXT: srli a5, a5, 56
-; LMULMAX1-RV64-NEXT: addi a5, a5, -56
+; LMULMAX1-RV64-NEXT: addiw a5, a5, -56
; LMULMAX1-RV64-NEXT: sb a5, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 31(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; LMULMAX2-RV64-NEXT: addi a5, a5, 257
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 30(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 28(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 26(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 24(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 22(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 20(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 18(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
; LMULMAX1-RV64-NEXT: addi a5, a5, 257
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 30(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 26(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 22(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 20(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; LMULMAX2-RV64-NEXT: addi a4, a4, 257
; LMULMAX2-RV64-NEXT: mul a5, a5, a4
; LMULMAX2-RV64-NEXT: srli a5, a5, 56
-; LMULMAX2-RV64-NEXT: addi a5, a5, -32
+; LMULMAX2-RV64-NEXT: addiw a5, a5, -32
; LMULMAX2-RV64-NEXT: sw a5, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 28(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 24(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 20(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
; LMULMAX1-RV64-NEXT: addi a4, a4, 257
; LMULMAX1-RV64-NEXT: mul a5, a5, a4
; LMULMAX1-RV64-NEXT: srli a5, a5, 56
-; LMULMAX1-RV64-NEXT: addi a5, a5, -32
+; LMULMAX1-RV64-NEXT: addiw a5, a5, -32
; LMULMAX1-RV64-NEXT: sw a5, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; LMULMAX2-RV64-NEXT: addi a5, a5, 257
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m2, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 31
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 63(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 30
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 62(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 29
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 61(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 28
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 60(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 27
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 59(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 26
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 58(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 25
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 57(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 24
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 56(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 23
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 55(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 22
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 54(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 21
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 53(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 20
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 52(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 19
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 51(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 18
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 50(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 17
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 49(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 16
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 48(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 47(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 46(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 45(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 44(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 43(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 42(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 41(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 40(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 39(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 38(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 37(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 36(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 35(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 34(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -56
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 33(sp)
; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
; LMULMAX1-RV64-NEXT: addi a5, a5, 257
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 15
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 47(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 14
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 46(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 13
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 45(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 12
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 44(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 11
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 43(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 10
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 42(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 9
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 41(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 8
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 40(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 39(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 38(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 37(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 36(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 35(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 34(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 33(sp)
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 16(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 31(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -56
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; LMULMAX2-RV64-NEXT: addi a5, a5, 257
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 62(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 60(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 58(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 56(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 54(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 52(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 50(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 48(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 46(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 44(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 42(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 40(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 38(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 36(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -48
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 34(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
; LMULMAX1-RV64-NEXT: addi a1, a1, 257
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 46(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 44(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 42(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 40(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 38(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 36(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 34(sp)
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 16(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 30(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 26(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 22(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
-; LMULMAX1-RV64-NEXT: addi a2, a2, -48
+; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 20(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -48
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; LMULMAX2-RV64-NEXT: addi a4, a4, 257
; LMULMAX2-RV64-NEXT: mul a5, a5, a4
; LMULMAX2-RV64-NEXT: srli a5, a5, 56
-; LMULMAX2-RV64-NEXT: addi a5, a5, -32
+; LMULMAX2-RV64-NEXT: addiw a5, a5, -32
; LMULMAX2-RV64-NEXT: sw a5, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 60(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 56(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 52(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 48(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 44(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 40(sp)
; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX2-RV64-NEXT: and a1, a1, a3
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
-; LMULMAX2-RV64-NEXT: addi a1, a1, -32
+; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 36(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
; LMULMAX1-RV64-NEXT: addi a5, a5, 257
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 44(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 40(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 36(sp)
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
-; LMULMAX1-RV64-NEXT: addi a1, a1, -32
+; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: srai a1, a1, 48
; RV64I-NEXT: add a0, a0, a1
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: srai a1, a1, 56
; RV64I-NEXT: add a0, a0, a1
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 60
; RV64I-NEXT: srai a0, a0, 60
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 60
; RV64I-NEXT: srai a1, a1, 60
; RV64I-NEXT: add a0, a0, a1
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: slli a0, a0, 60
; RV64IZbb-NEXT: srai a0, a0, 60
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: slli a1, a1, 60
; RV64IZbb-NEXT: srai a1, a1, 60
; RV64IZbb-NEXT: add a0, a0, a1
; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s0, a0
; RV64-NEXT: call bar@plt
-; RV64-NEXT: add a1, s3, s1
-; RV64-NEXT: add a0, s0, a0
+; RV64-NEXT: addw a1, s3, s1
+; RV64-NEXT: addw a0, s0, a0
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
;
; RV64I-LABEL: sll_redundant_mask_zeros:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: slliw a1, a1, 1
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %b, 1
;
; RV64I-LABEL: srl_redundant_mask_zeros:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: slliw a1, a1, 2
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %b, 2
;
; RV64I-LABEL: sra_redundant_mask_zeros:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a1, 3
+; RV64I-NEXT: slliw a1, a1, 3
; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %b, 3
; RV64IM-NEXT: addw a1, a1, a0
; RV64IM-NEXT: srliw a2, a1, 31
; RV64IM-NEXT: srli a1, a1, 6
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 95
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %x, 95
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 40
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 1060
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %x, 1060
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 40
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: addi a2, zero, -723
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %x, -723
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 40
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: lui a2, 1048570
; RV64IM-NEXT: addiw a2, a2, 1595
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %x, -22981
; RV64IM-NEXT: addiw a2, a2, 389
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 32
-; RV64IM-NEXT: addw a2, a1, a0
-; RV64IM-NEXT: srliw a2, a2, 31
-; RV64IM-NEXT: add a1, a1, a0
+; RV64IM-NEXT: addw a1, a1, a0
+; RV64IM-NEXT: srliw a2, a1, 31
; RV64IM-NEXT: sraiw a1, a1, 6
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: addw a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 95
-; RV64IM-NEXT: mul a2, a1, a2
-; RV64IM-NEXT: sub a0, a0, a2
+; RV64IM-NEXT: mulw a2, a1, a2
+; RV64IM-NEXT: subw a0, a0, a2
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = srem i32 %x, 95
; RV64-NEXT: and a3, a3, a4
; RV64-NEXT: srli a3, a3, 32
; RV64-NEXT: sb a3, 12(s0)
-; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: slliw a1, a1, 2
; RV64-NEXT: srli a3, s4, 31
; RV64-NEXT: and a2, a2, a3
; RV64-NEXT: srli a4, a2, 31
-; RV64-NEXT: sub a1, a4, a1
+; RV64-NEXT: subw a1, a4, a1
; RV64-NEXT: sw a1, 8(s0)
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: slli a1, a2, 33
; RV64M-NEXT: and a4, a4, a5
; RV64M-NEXT: srli a4, a4, 32
; RV64M-NEXT: sb a4, 12(a0)
-; RV64M-NEXT: slli a2, a2, 2
+; RV64M-NEXT: slliw a2, a2, 2
; RV64M-NEXT: srli a4, a6, 31
; RV64M-NEXT: and a1, a1, a4
; RV64M-NEXT: srli a5, a1, 31
-; RV64M-NEXT: sub a2, a5, a2
+; RV64M-NEXT: subw a2, a5, a2
; RV64M-NEXT: sw a2, 8(a0)
; RV64M-NEXT: slli a1, a1, 33
; RV64M-NEXT: and a2, a3, a4
; RV64IM-NEXT: add a5, a5, a1
; RV64IM-NEXT: srli a2, a5, 63
; RV64IM-NEXT: srli a5, a5, 6
-; RV64IM-NEXT: add a2, a5, a2
+; RV64IM-NEXT: addw a2, a5, a2
; RV64IM-NEXT: addi a5, zero, 95
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a1, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a1, a1, a2
; RV64IM-NEXT: lui a2, 777976
; RV64IM-NEXT: addiw a2, a2, -1057
; RV64IM-NEXT: slli a2, a2, 15
; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: srli a5, a2, 63
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: add a2, a2, a5
+; RV64IM-NEXT: addw a2, a2, a5
; RV64IM-NEXT: addi a5, zero, -124
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a2, a4, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a2, a4, a2
; RV64IM-NEXT: lui a4, 2675
; RV64IM-NEXT: addiw a4, a4, -251
; RV64IM-NEXT: slli a4, a4, 13
; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 5
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: addi a5, zero, 98
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: lui a4, 1040212
; RV64IM-NEXT: addiw a4, a4, 1977
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: mulh a4, a6, a4
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 7
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: addi a5, zero, -1003
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a4, a6, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a4, a6, a4
; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: add a2, a2, a1
; RV64IM-NEXT: srli a3, a2, 63
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: add a2, a2, a3
+; RV64IM-NEXT: addw a2, a2, a3
; RV64IM-NEXT: addi a3, zero, 95
-; RV64IM-NEXT: mul a2, a2, a3
-; RV64IM-NEXT: sub t0, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a3
+; RV64IM-NEXT: subw t0, a1, a2
; RV64IM-NEXT: mulh a2, a4, a5
; RV64IM-NEXT: add a2, a2, a4
; RV64IM-NEXT: srli a1, a2, 63
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: add a1, a2, a1
-; RV64IM-NEXT: mul a1, a1, a3
-; RV64IM-NEXT: sub a1, a4, a1
+; RV64IM-NEXT: addw a1, a2, a1
+; RV64IM-NEXT: mulw a1, a1, a3
+; RV64IM-NEXT: subw a1, a4, a1
; RV64IM-NEXT: mulh a2, a7, a5
; RV64IM-NEXT: add a2, a2, a7
; RV64IM-NEXT: srli a4, a2, 63
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: add a2, a2, a4
-; RV64IM-NEXT: mul a2, a2, a3
-; RV64IM-NEXT: sub a2, a7, a2
+; RV64IM-NEXT: addw a2, a2, a4
+; RV64IM-NEXT: mulw a2, a2, a3
+; RV64IM-NEXT: subw a2, a7, a2
; RV64IM-NEXT: mulh a4, a6, a5
; RV64IM-NEXT: add a4, a4, a6
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 6
-; RV64IM-NEXT: add a4, a4, a5
-; RV64IM-NEXT: mul a3, a4, a3
-; RV64IM-NEXT: sub a3, a6, a3
+; RV64IM-NEXT: addw a4, a4, a5
+; RV64IM-NEXT: mulw a3, a4, a3
+; RV64IM-NEXT: subw a3, a6, a3
; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0)
; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __divdi3@plt
-; RV64I-NEXT: add a0, s8, a0
-; RV64I-NEXT: add a1, s7, s1
-; RV64I-NEXT: add a2, s6, s4
-; RV64I-NEXT: add a3, s5, s9
+; RV64I-NEXT: addw a0, s8, a0
+; RV64I-NEXT: addw a1, s7, s1
+; RV64I-NEXT: addw a2, s6, s4
+; RV64I-NEXT: addw a3, s5, s9
; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0)
; RV64IM-NEXT: add a2, a2, a1
; RV64IM-NEXT: srli a3, a2, 63
; RV64IM-NEXT: srai a2, a2, 6
-; RV64IM-NEXT: add t3, a2, a3
+; RV64IM-NEXT: addw t3, a2, a3
; RV64IM-NEXT: addi t0, zero, 95
-; RV64IM-NEXT: mul a3, t3, t0
-; RV64IM-NEXT: sub t1, a1, a3
+; RV64IM-NEXT: mulw a3, t3, t0
+; RV64IM-NEXT: subw t1, a1, a3
; RV64IM-NEXT: mulh a3, a4, a5
; RV64IM-NEXT: add a3, a3, a4
; RV64IM-NEXT: srli a1, a3, 63
; RV64IM-NEXT: srai a3, a3, 6
-; RV64IM-NEXT: add a1, a3, a1
-; RV64IM-NEXT: mul a3, a1, t0
-; RV64IM-NEXT: sub t2, a4, a3
+; RV64IM-NEXT: addw a1, a3, a1
+; RV64IM-NEXT: mulw a3, a1, t0
+; RV64IM-NEXT: subw t2, a4, a3
; RV64IM-NEXT: mulh a4, a7, a5
; RV64IM-NEXT: add a4, a4, a7
; RV64IM-NEXT: srli a3, a4, 63
; RV64IM-NEXT: srai a4, a4, 6
-; RV64IM-NEXT: add a3, a4, a3
-; RV64IM-NEXT: mul a4, a3, t0
-; RV64IM-NEXT: sub a4, a7, a4
+; RV64IM-NEXT: addw a3, a4, a3
+; RV64IM-NEXT: mulw a4, a3, t0
+; RV64IM-NEXT: subw a4, a7, a4
; RV64IM-NEXT: mulh a5, a6, a5
; RV64IM-NEXT: add a5, a5, a6
; RV64IM-NEXT: srli a2, a5, 63
; RV64IM-NEXT: srai a5, a5, 6
-; RV64IM-NEXT: add a2, a5, a2
-; RV64IM-NEXT: mul a5, a2, t0
-; RV64IM-NEXT: sub a5, a6, a5
-; RV64IM-NEXT: add a2, a5, a2
-; RV64IM-NEXT: add a3, a4, a3
-; RV64IM-NEXT: add a1, t2, a1
-; RV64IM-NEXT: add a4, t1, t3
+; RV64IM-NEXT: addw a2, a5, a2
+; RV64IM-NEXT: mulw a5, a2, t0
+; RV64IM-NEXT: subw a5, a6, a5
+; RV64IM-NEXT: addw a2, a5, a2
+; RV64IM-NEXT: addw a3, a4, a3
+; RV64IM-NEXT: addw a1, t2, a1
+; RV64IM-NEXT: addw a4, t1, t3
; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0)
; RV64I-NEXT: srli a4, a2, 58
; RV64I-NEXT: add a4, a2, a4
; RV64I-NEXT: andi a4, a4, -64
-; RV64I-NEXT: sub s2, a2, a4
+; RV64I-NEXT: subw s2, a2, a4
; RV64I-NEXT: srli a2, a1, 59
; RV64I-NEXT: add a2, a1, a2
; RV64I-NEXT: andi a2, a2, -32
-; RV64I-NEXT: sub s3, a1, a2
+; RV64I-NEXT: subw s3, a1, a2
; RV64I-NEXT: srli a1, a3, 61
; RV64I-NEXT: add a1, a3, a1
; RV64I-NEXT: andi a1, a1, -8
-; RV64I-NEXT: sub s1, a3, a1
+; RV64I-NEXT: subw s1, a3, a1
; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s0)
; RV64IM-NEXT: add a5, a5, a1
; RV64IM-NEXT: srli a2, a5, 63
; RV64IM-NEXT: srli a5, a5, 6
-; RV64IM-NEXT: add a2, a5, a2
+; RV64IM-NEXT: addw a2, a5, a2
; RV64IM-NEXT: addi a5, zero, 95
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a1, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a1, a1, a2
; RV64IM-NEXT: srli a2, a4, 58
; RV64IM-NEXT: add a2, a4, a2
; RV64IM-NEXT: andi a2, a2, -64
-; RV64IM-NEXT: sub a2, a4, a2
+; RV64IM-NEXT: subw a2, a4, a2
; RV64IM-NEXT: srli a4, a3, 59
; RV64IM-NEXT: add a4, a3, a4
; RV64IM-NEXT: andi a4, a4, -32
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: srli a4, a6, 61
; RV64IM-NEXT: add a4, a6, a4
; RV64IM-NEXT: andi a4, a4, -8
-; RV64IM-NEXT: sub a4, a6, a4
+; RV64IM-NEXT: subw a4, a6, a4
; RV64IM-NEXT: sh a4, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: add a4, a4, a1
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 4
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: addi a5, zero, 23
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a1, a1, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a1, a1, a4
; RV64IM-NEXT: lui a4, 6413
; RV64IM-NEXT: addiw a4, a4, 1265
; RV64IM-NEXT: slli a4, a4, 13
; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 8
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: addi a5, zero, 654
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: lui a4, 12375
; RV64IM-NEXT: addiw a4, a4, -575
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: mulh a4, a2, a4
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 11
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a2, a2, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a3, 2(a0)
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: lui a3, 8
; RV64I-NEXT: and a1, a1, a3
-; RV64I-NEXT: sub s3, a2, a1
+; RV64I-NEXT: subw s3, a2, a1
; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0
; RV64IM-NEXT: add a4, a4, a1
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 4
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: addi a5, zero, 23
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a1, a1, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a1, a1, a4
; RV64IM-NEXT: lui a4, 12375
; RV64IM-NEXT: addiw a4, a4, -575
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: srli a5, a4, 63
; RV64IM-NEXT: srli a4, a4, 11
-; RV64IM-NEXT: add a4, a4, a5
+; RV64IM-NEXT: addw a4, a4, a5
; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: srli a4, a2, 49
; RV64IM-NEXT: add a4, a2, a4
; RV64IM-NEXT: lui a5, 8
; RV64IM-NEXT: and a4, a4, a5
-; RV64IM-NEXT: sub a2, a2, a4
+; RV64IM-NEXT: subw a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: sh a3, 6(a0)
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: srai a1, a1, 48
; RV64I-NEXT: sub a0, a0, a1
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: srai a1, a1, 56
; RV64I-NEXT: sub a0, a0, a1
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 60
; RV64I-NEXT: srai a0, a0, 60
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 60
; RV64I-NEXT: srai a1, a1, 60
; RV64I-NEXT: sub a0, a0, a1
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: slli a0, a0, 60
; RV64IZbb-NEXT: srai a0, a0, 60
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: slli a1, a1, 60
; RV64IZbb-NEXT: srai a1, a1, 60
; RV64IZbb-NEXT: sub a0, a0, a1
;
; RV64I-LABEL: func32:
; RV64I: # %bb.0:
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: addw a1, a0, a1
; RV64I-NEXT: sext.w a2, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64IM-NEXT: addiw a2, a2, 777
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 32
-; RV64IM-NEXT: sub a2, a0, a1
+; RV64IM-NEXT: subw a2, a0, a1
; RV64IM-NEXT: srliw a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = urem i32 %x, 95
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 42
; RV64IM-NEXT: addi a2, zero, 1060
-; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: mulw a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
%1 = urem i32 %x, 1060
; RV64IM-NEXT: addiw a2, a2, 777
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 32
-; RV64IM-NEXT: sub a2, a0, a1
+; RV64IM-NEXT: subw a2, a0, a1
; RV64IM-NEXT: srliw a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95
-; RV64IM-NEXT: mul a2, a1, a2
-; RV64IM-NEXT: sub a0, a0, a2
+; RV64IM-NEXT: mulw a2, a1, a2
+; RV64IM-NEXT: subw a0, a0, a2
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = urem i32 %x, 95
; RV64IM-NEXT: add a2, a2, a5
; RV64IM-NEXT: srli a2, a2, 6
; RV64IM-NEXT: addi a5, zero, 95
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a1, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a1, a1, a2
; RV64IM-NEXT: srli a2, a4, 2
; RV64IM-NEXT: lui a5, 264
; RV64IM-NEXT: addiw a5, a5, 1057
; RV64IM-NEXT: mulhu a2, a2, a5
; RV64IM-NEXT: srli a2, a2, 3
; RV64IM-NEXT: addi a5, zero, 124
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a2, a4, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a2, a4, a2
; RV64IM-NEXT: srli a4, a3, 1
; RV64IM-NEXT: lui a5, 2675
; RV64IM-NEXT: addiw a5, a5, -251
; RV64IM-NEXT: mulhu a4, a4, a5
; RV64IM-NEXT: srli a4, a4, 4
; RV64IM-NEXT: addi a5, zero, 98
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: lui a4, 8364
; RV64IM-NEXT: addiw a4, a4, -1977
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: mulhu a4, a6, a4
; RV64IM-NEXT: srli a4, a4, 7
; RV64IM-NEXT: addi a5, zero, 1003
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a4, a6, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a4, a6, a4
; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: add a2, a3, a2
; RV64IM-NEXT: srli a2, a2, 6
; RV64IM-NEXT: addi a3, zero, 95
-; RV64IM-NEXT: mul a2, a2, a3
-; RV64IM-NEXT: sub t0, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a3
+; RV64IM-NEXT: subw t0, a1, a2
; RV64IM-NEXT: mulhu a2, a4, a5
; RV64IM-NEXT: sub a1, a4, a2
; RV64IM-NEXT: srli a1, a1, 1
; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 6
-; RV64IM-NEXT: mul a1, a1, a3
-; RV64IM-NEXT: sub a1, a4, a1
+; RV64IM-NEXT: mulw a1, a1, a3
+; RV64IM-NEXT: subw a1, a4, a1
; RV64IM-NEXT: mulhu a2, a7, a5
; RV64IM-NEXT: sub a4, a7, a2
; RV64IM-NEXT: srli a4, a4, 1
; RV64IM-NEXT: add a2, a4, a2
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: mul a2, a2, a3
-; RV64IM-NEXT: sub a2, a7, a2
+; RV64IM-NEXT: mulw a2, a2, a3
+; RV64IM-NEXT: subw a2, a7, a2
; RV64IM-NEXT: mulhu a4, a6, a5
; RV64IM-NEXT: sub a5, a6, a4
; RV64IM-NEXT: srli a5, a5, 1
; RV64IM-NEXT: add a4, a5, a4
; RV64IM-NEXT: srli a4, a4, 6
-; RV64IM-NEXT: mul a3, a4, a3
-; RV64IM-NEXT: sub a3, a6, a3
+; RV64IM-NEXT: mulw a3, a4, a3
+; RV64IM-NEXT: subw a3, a6, a3
; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0)
; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __udivdi3@plt
-; RV64I-NEXT: add a0, s8, a0
-; RV64I-NEXT: add a1, s7, s1
-; RV64I-NEXT: add a2, s6, s4
-; RV64I-NEXT: add a3, s5, s9
+; RV64I-NEXT: addw a0, s8, a0
+; RV64I-NEXT: addw a1, s7, s1
+; RV64I-NEXT: addw a2, s6, s4
+; RV64I-NEXT: addw a3, s5, s9
; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0)
; RV64IM-NEXT: add a2, a3, a2
; RV64IM-NEXT: srli t3, a2, 6
; RV64IM-NEXT: addi t0, zero, 95
-; RV64IM-NEXT: mul a3, t3, t0
-; RV64IM-NEXT: sub t1, a1, a3
+; RV64IM-NEXT: mulw a3, t3, t0
+; RV64IM-NEXT: subw t1, a1, a3
; RV64IM-NEXT: mulhu a3, a4, a5
; RV64IM-NEXT: sub a1, a4, a3
; RV64IM-NEXT: srli a1, a1, 1
; RV64IM-NEXT: add a1, a1, a3
; RV64IM-NEXT: srli a1, a1, 6
-; RV64IM-NEXT: mul a3, a1, t0
-; RV64IM-NEXT: sub t2, a4, a3
+; RV64IM-NEXT: mulw a3, a1, t0
+; RV64IM-NEXT: subw t2, a4, a3
; RV64IM-NEXT: mulhu a4, a7, a5
; RV64IM-NEXT: sub a3, a7, a4
; RV64IM-NEXT: srli a3, a3, 1
; RV64IM-NEXT: add a3, a3, a4
; RV64IM-NEXT: srli a3, a3, 6
-; RV64IM-NEXT: mul a4, a3, t0
-; RV64IM-NEXT: sub a4, a7, a4
+; RV64IM-NEXT: mulw a4, a3, t0
+; RV64IM-NEXT: subw a4, a7, a4
; RV64IM-NEXT: mulhu a5, a6, a5
; RV64IM-NEXT: sub a2, a6, a5
; RV64IM-NEXT: srli a2, a2, 1
; RV64IM-NEXT: add a2, a2, a5
; RV64IM-NEXT: srli a2, a2, 6
-; RV64IM-NEXT: mul a5, a2, t0
-; RV64IM-NEXT: sub a5, a6, a5
-; RV64IM-NEXT: add a2, a5, a2
-; RV64IM-NEXT: add a3, a4, a3
-; RV64IM-NEXT: add a1, t2, a1
-; RV64IM-NEXT: add a4, t1, t3
+; RV64IM-NEXT: mulw a5, a2, t0
+; RV64IM-NEXT: subw a5, a6, a5
+; RV64IM-NEXT: addw a2, a5, a2
+; RV64IM-NEXT: addw a3, a4, a3
+; RV64IM-NEXT: addw a1, t2, a1
+; RV64IM-NEXT: addw a4, t1, t3
; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: add a2, a2, a5
; RV64IM-NEXT: srli a2, a2, 6
; RV64IM-NEXT: addi a5, zero, 95
-; RV64IM-NEXT: mul a2, a2, a5
-; RV64IM-NEXT: sub a1, a1, a2
+; RV64IM-NEXT: mulw a2, a2, a5
+; RV64IM-NEXT: subw a1, a1, a2
; RV64IM-NEXT: andi a2, a4, 63
; RV64IM-NEXT: andi a3, a3, 31
; RV64IM-NEXT: andi a4, a6, 7
; RV64IM-NEXT: add a4, a5, a4
; RV64IM-NEXT: srli a4, a4, 4
; RV64IM-NEXT: addi a5, zero, 23
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a1, a1, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a1, a1, a4
; RV64IM-NEXT: srli a4, a3, 1
; RV64IM-NEXT: lui a5, 6413
; RV64IM-NEXT: addiw a5, a5, 1265
; RV64IM-NEXT: mulhu a4, a4, a5
; RV64IM-NEXT: srli a4, a4, 7
; RV64IM-NEXT: addi a5, zero, 654
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a3, a3, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a3, a3, a4
; RV64IM-NEXT: lui a4, 1044567
; RV64IM-NEXT: addiw a4, a4, -575
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: srli a4, a4, 12
; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327
-; RV64IM-NEXT: mul a4, a4, a5
-; RV64IM-NEXT: sub a2, a2, a4
+; RV64IM-NEXT: mulw a4, a4, a5
+; RV64IM-NEXT: subw a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a3, 2(a0)
;
; RV64I-LABEL: func32:
; RV64I: # %bb.0:
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: subw a1, a0, a1
; RV64I-NEXT: sext.w a2, a0
; RV64I-NEXT: mv a0, zero
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2
+; LP64-LP64F-LP64D-FPELIM-NEXT: addw a1, a1, s0
+; LP64-LP64F-LP64D-FPELIM-NEXT: addw a1, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1
-; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2
+; LP64-LP64F-LP64D-WITHFP-NEXT: addw a1, a1, s1
+; LP64-LP64F-LP64D-WITHFP-NEXT: addw a1, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
;
; RV64-LABEL: uaddo.i32:
; RV64: # %bb.0: # %entry
-; RV64-NEXT: addw a3, a0, a1
-; RV64-NEXT: sext.w a4, a0
-; RV64-NEXT: sltu a3, a3, a4
-; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: sw a0, 0(a2)
-; RV64-NEXT: mv a0, a3
+; RV64-NEXT: addw a1, a0, a1
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: sltu a0, a1, a0
+; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: uaddo.i32:
;
; RV64ZBA-LABEL: uaddo.i32:
; RV64ZBA: # %bb.0: # %entry
-; RV64ZBA-NEXT: addw a3, a0, a1
-; RV64ZBA-NEXT: sext.w a4, a0
-; RV64ZBA-NEXT: sltu a3, a3, a4
-; RV64ZBA-NEXT: add a0, a0, a1
-; RV64ZBA-NEXT: sw a0, 0(a2)
-; RV64ZBA-NEXT: mv a0, a3
+; RV64ZBA-NEXT: addw a1, a0, a1
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: sltu a0, a1, a0
+; RV64ZBA-NEXT: sw a1, 0(a2)
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
; RV64: # %bb.0: # %entry
; RV64-NEXT: sext.w a2, a0
; RV64-NEXT: addiw a3, a0, -2
-; RV64-NEXT: sltu a2, a3, a2
-; RV64-NEXT: addi a0, a0, -2
-; RV64-NEXT: sw a0, 0(a1)
-; RV64-NEXT: mv a0, a2
+; RV64-NEXT: sltu a0, a3, a2
+; RV64-NEXT: sw a3, 0(a1)
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: uaddo.i32.constant:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: sext.w a2, a0
; RV64ZBA-NEXT: addiw a3, a0, -2
-; RV64ZBA-NEXT: sltu a2, a3, a2
-; RV64ZBA-NEXT: addi a0, a0, -2
-; RV64ZBA-NEXT: sw a0, 0(a1)
-; RV64ZBA-NEXT: mv a0, a2
+; RV64ZBA-NEXT: sltu a0, a3, a2
+; RV64ZBA-NEXT: sw a3, 0(a1)
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 -2)
;
; RV64-LABEL: usubo.i32:
; RV64: # %bb.0: # %entry
-; RV64-NEXT: subw a3, a0, a1
-; RV64-NEXT: sext.w a4, a0
-; RV64-NEXT: sltu a3, a4, a3
-; RV64-NEXT: sub a0, a0, a1
-; RV64-NEXT: sw a0, 0(a2)
-; RV64-NEXT: mv a0, a3
+; RV64-NEXT: subw a1, a0, a1
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: sw a1, 0(a2)
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.i32:
;
; RV64ZBA-LABEL: usubo.i32:
; RV64ZBA: # %bb.0: # %entry
-; RV64ZBA-NEXT: subw a3, a0, a1
-; RV64ZBA-NEXT: sext.w a4, a0
-; RV64ZBA-NEXT: sltu a3, a4, a3
-; RV64ZBA-NEXT: sub a0, a0, a1
-; RV64ZBA-NEXT: sw a0, 0(a2)
-; RV64ZBA-NEXT: mv a0, a3
+; RV64ZBA-NEXT: subw a1, a0, a1
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: sltu a0, a0, a1
+; RV64ZBA-NEXT: sw a1, 0(a2)
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
; RV64-LABEL: usubo.i32.constant.rhs:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addiw a2, a0, 2
-; RV64-NEXT: sext.w a3, a0
-; RV64-NEXT: sltu a2, a3, a2
-; RV64-NEXT: addi a0, a0, 2
-; RV64-NEXT: sw a0, 0(a1)
-; RV64-NEXT: mv a0, a2
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: sltu a0, a0, a2
+; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.i32.constant.rhs:
; RV64ZBA-LABEL: usubo.i32.constant.rhs:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addiw a2, a0, 2
-; RV64ZBA-NEXT: sext.w a3, a0
-; RV64ZBA-NEXT: sltu a2, a3, a2
-; RV64ZBA-NEXT: addi a0, a0, 2
-; RV64ZBA-NEXT: sw a0, 0(a1)
-; RV64ZBA-NEXT: mv a0, a2
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: sltu a0, a0, a2
+; RV64ZBA-NEXT: sw a2, 0(a1)
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 -2)
;
; RV64-LABEL: usubo.i32.constant.lhs:
; RV64: # %bb.0: # %entry
-; RV64-NEXT: addi a3, zero, -2
-; RV64-NEXT: subw a2, a3, a0
-; RV64-NEXT: addi a2, a2, 1
-; RV64-NEXT: seqz a2, a2
-; RV64-NEXT: sub a0, a3, a0
-; RV64-NEXT: sw a0, 0(a1)
-; RV64-NEXT: mv a0, a2
+; RV64-NEXT: addi a2, zero, -2
+; RV64-NEXT: subw a2, a2, a0
+; RV64-NEXT: addi a0, a2, 1
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: sw a2, 0(a1)
; RV64-NEXT: ret
;
; RV32ZBA-LABEL: usubo.i32.constant.lhs:
;
; RV64ZBA-LABEL: usubo.i32.constant.lhs:
; RV64ZBA: # %bb.0: # %entry
-; RV64ZBA-NEXT: addi a3, zero, -2
-; RV64ZBA-NEXT: subw a2, a3, a0
-; RV64ZBA-NEXT: addi a2, a2, 1
-; RV64ZBA-NEXT: seqz a2, a2
-; RV64ZBA-NEXT: sub a0, a3, a0
-; RV64ZBA-NEXT: sw a0, 0(a1)
-; RV64ZBA-NEXT: mv a0, a2
+; RV64ZBA-NEXT: addi a2, zero, -2
+; RV64ZBA-NEXT: subw a2, a2, a0
+; RV64ZBA-NEXT: addi a0, a2, 1
+; RV64ZBA-NEXT: seqz a0, a0
+; RV64ZBA-NEXT: sw a2, 0(a1)
; RV64ZBA-NEXT: ret
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -2, i32 %v1)