radeonsi: compute how many input VGPRs fragment shaders have
authorMarek Olšák <marek.olsak@amd.com>
Sun, 3 Jan 2016 02:26:28 +0000 (03:26 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Sun, 21 Feb 2016 20:08:57 +0000 (21:08 +0100)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h

index 1145f89..6558941 100644 (file)
@@ -4537,6 +4537,47 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 
        radeon_llvm_dispose(&ctx.radeon_bld);
 
+       /* Calculate the number of fragment input VGPRs. */
+       if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
+               shader->num_input_vgprs = 0;
+               shader->face_vgpr_index = -1;
+
+               if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 3;
+               if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 2;
+               if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
+                       shader->face_vgpr_index = shader->num_input_vgprs;
+                       shader->num_input_vgprs += 1;
+               }
+               if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+               if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
+                       shader->num_input_vgprs += 1;
+       }
+
        if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
                shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
                shader->gs_copy_shader->selector = shader->selector;
index 131455b..3be24f3 100644 (file)
@@ -281,6 +281,8 @@ struct si_shader {
 
        ubyte                   num_input_sgprs;
        ubyte                   num_input_vgprs;
+       char                    face_vgpr_index;
+
        unsigned                vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
        bool                    uses_instanceid;
        unsigned                nr_pos_exports;