def rvv_vnot : PatFrag<(ops node:$in),
(xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
-class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
- dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
-}
-
multiclass VPatUSLoadStoreSDNode<ValueType type,
int log2sew,
LMULInfo vlmul,
fvti.AVL, fvti.Log2SEW)>;
}
-multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
- string instruction_name,
- bit swap = 0> {
+multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
+ CondCode cc> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2), cc)),
- SwapHelper<(instruction),
- (instruction vti.RegClass:$rs1),
- (instruction vti.RegClass:$rs2),
- (instruction vti.AVL, vti.Log2SEW),
- swap>.Value>;
+ (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+ vti.Log2SEW)>;
+ }
+}
+
+multiclass VPatIntegerSetCCSDNode_VV_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCSDNode_VV<instruction_name, cc> {
+ foreach vti = AllIntegerVectors in {
+ defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
+ def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs2),
+ (vti.Vector vti.RegClass:$rs1), invcc)),
+ (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+ vti.Log2SEW)>;
}
}
-multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
+multiclass VPatIntegerSetCCSDNode_XI<
string instruction_name,
+ CondCode cc,
string kind,
ComplexPattern SplatPatKind,
- DAGOperand xop_kind,
- bit swap = 0> {
+ DAGOperand xop_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
- SwapHelper<(instruction),
- (instruction vti.RegClass:$rs1),
- (instruction xop_kind:$rs2),
- (instruction vti.AVL, vti.Log2SEW),
- swap>.Value>;
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
}
}
-multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
- SplatPat_simm5, simm5, swap>;
+multiclass VPatIntegerSetCCSDNode_XI_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc,
+ string kind,
+ ComplexPattern SplatPatKind,
+ DAGOperand xop_kind>
+ : VPatIntegerSetCCSDNode_XI<instruction_name, cc, kind, SplatPatKind,
+ xop_kind> {
+ foreach vti = AllIntegerVectors in {
+ defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
+ def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+ (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
+ def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)),
+ (vti.Vector vti.RegClass:$rs1), invcc)),
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
+ }
}
-multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
-}
+multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
+ SplatPat, GPR>;
-multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
- SplatPat_simm5, simm5, swap>;
-}
+multiclass VPatIntegerSetCCSDNode_VI<string instruction_name, CondCode cc>
+ : VPatIntegerSetCCSDNode_XI<instruction_name, cc, "VI", SplatPat_simm5, simm5>;
-multiclass VPatIntegerSetCCSDNode_VIPlus1<CondCode cc, string instruction_name,
+multiclass VPatIntegerSetCCSDNode_VIPlus1<string instruction_name, CondCode cc,
ComplexPattern splatpat_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
}
// 12.8. Vector Integer Comparison Instructions
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
-
-defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
-defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
+
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
+// There is no VMSGE(U)_VX instruction
+
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ", SETEQ>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSNE", SETNE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLE", SETLE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGT", SETGT>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
+
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
SplatPat_simm5_plus1_nonzero>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
SplatPat_simm5_plus1_nonzero>;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
-
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETGE, "PseudoVMSGT",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
SplatPat_simm5_plus1_nonzero>;
// 12.9. Vector Integer Min/Max Instructions
// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
- CondCode cc, CondCode invcc> :
- VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc,
(vti.Mask V0),
; RV32D-LABEL: cttz_nxv1i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64D-LABEL: cttz_nxv1i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32D-LABEL: cttz_nxv2i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64D-LABEL: cttz_nxv2i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32D-LABEL: cttz_nxv4i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64D-LABEL: cttz_nxv4i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32D-LABEL: cttz_nxv8i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64D-LABEL: cttz_nxv8i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32D-LABEL: cttz_nxv16i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; RV32D-NEXT: vmv.v.i v10, 0
-; RV32D-NEXT: vmseq.vv v0, v10, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV64D-LABEL: cttz_nxv16i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; RV32D-LABEL: cttz_nxv1i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-LABEL: cttz_nxv1i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-LABEL: cttz_nxv2i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-LABEL: cttz_nxv2i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV32D-LABEL: cttz_nxv4i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-LABEL: cttz_nxv4i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV32D-LABEL: cttz_nxv8i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV32D-NEXT: vmv.v.i v10, 0
-; RV32D-NEXT: vmseq.vv v0, v10, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-LABEL: cttz_nxv8i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV32D-LABEL: cttz_nxv16i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV32D-NEXT: vmv.v.i v12, 0
-; RV32D-NEXT: vmseq.vv v0, v12, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-LABEL: cttz_nxv16i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV64D-NEXT: vmv.v.i v12, 0
-; RV64D-NEXT: vmseq.vv v0, v12, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; RV64D-LABEL: cttz_nxv1i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
; RV64D-LABEL: cttz_nxv2i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
; RV64D-LABEL: cttz_nxv4i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
; RV64D-LABEL: cttz_nxv8i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV64D-NEXT: vmv.v.i v12, 0
-; RV64D-NEXT: vmseq.vv v0, v12, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
; CHECK-LABEL: icmp_eq_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmseq.vv v0, v9, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ne_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsne.vv v0, v9, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v9
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_uge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v9
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ult_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v9, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v9
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v9
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_slt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v9, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_eq_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmseq.vv v0, v10, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ne_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsne.vv v0, v10, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v10
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_uge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v10
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ult_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v10, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v10
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v10
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_slt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v10, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_eq_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmseq.vv v0, v12, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ne_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsne.vv v0, v12, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v12
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_uge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v12
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_ult_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v12, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v12
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_sge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v12
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-LABEL: icmp_slt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v12, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_eq_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmseq.vv v0, v16, v8
+; RV64-NEXT: vmseq.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_ne_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsne.vv v0, v16, v8
+; RV64-NEXT: vmsne.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_ugt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsltu.vv v0, v8, v16
+; RV64-NEXT: vmsltu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_uge_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsleu.vv v0, v8, v16
+; RV64-NEXT: vmsleu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_ult_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsltu.vv v0, v16, v8
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_sgt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmslt.vv v0, v8, v16
+; RV64-NEXT: vmslt.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_sge_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsle.vv v0, v8, v16
+; RV64-NEXT: vmsle.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
; RV64-LABEL: icmp_slt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmslt.vv v0, v16, v8
+; RV64-NEXT: vmsgt.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
projects / platform / upstream / llvm.git / commitdiff