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MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC
author
David Daney
<david.daney@cavium.com>
Tue, 30 Aug 2011 13:45:20 +0000
(06:45 -0700)
committer
Ralf Baechle
<ralf@linux-mips.org>
Wed, 21 Sep 2011 15:54:02 +0000
(17:54 +0200)
Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/2753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/stackframe.h
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diff --git
a/arch/mips/include/asm/stackframe.h
b/arch/mips/include/asm/stackframe.h
index
b4ba244
..
cb41af5
100644
(file)
--- a/
arch/mips/include/asm/stackframe.h
+++ b/
arch/mips/include/asm/stackframe.h
@@
-195,9
+195,9
@@
* to cover the pipeline delay.
*/
.set mips32
- mfc0
v1
, CP0_TCSTATUS
+ mfc0
k0
, CP0_TCSTATUS
.set mips0
- LONG_S
v1
, PT_TCSTATUS(sp)
+ LONG_S
k0
, PT_TCSTATUS(sp)
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_S $4, PT_R4(sp)
LONG_S $5, PT_R5(sp)