def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
GISDNodeXFormEquiv<NegateImm>;
+
+def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
+ GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue());
}
+void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB,
+ const MachineInstr &MI) const {
+ const MachineOperand &Op = MI.getOperand(1);
+ if (MI.getOpcode() == TargetOpcode::G_FCONSTANT)
+ MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
+ else {
+ assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
+ MIB.addImm(Op.getCImm()->getSExtValue());
+ }
+}
+
bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const {
return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm());
}
void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &MI) const;
+ void renderBitcastImm(MachineInstrBuilder &MIB,
+ const MachineInstr &MI) const;
+
bool isInlineImmediate16(int64_t Imm) const;
bool isInlineImmediate32(int64_t Imm) const;
bool isInlineImmediate64(int64_t Imm) const;